Bit-Serial Neural Network Convolution for Low-Bitwidth Processing
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Solution Overview
Problem
Existing neural network processing methods are inefficient in terms of energy consumption and memory utilization, particularly in resource-constrained environments, due to the use of high bitwidth data operations.
Innovation Solution
Implementing a bitwise operation-based convolution method that converts weight kernels and input feature maps to bit serials, allowing for low bitwidth processing using bitwise operations, which reduces energy consumption and improves memory utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional convolution operations with high bitwidth are used, then processing accuracy is maintained, but energy consumption increases and memory utilization deteriorates
Solution Approach 1:
The patent segments the convolution operation into bitwise operations (AND, OR, XOR, popcount) operating on individual bits or small bit groups. Instead of processing full-precision floating-point numbers, the method divides weights and activations into bit representations and processes them separately through logical operations, thereby reducing energy consumption while maintaining computational accuracy through the accumulation of bit-level results.
Solution Approach 2:
The patent changes the numerical representation parameter from high-bitwidth floating-point format to low-bitwidth integer or bit representation. By representing weights and activations in binary format and performing operations at the bit level rather than at the full numerical precision level, the method reduces energy consumption and improves memory utilization while preserving processing accuracy through proper bit manipulation and result aggregation.
2Measurement precision
If traditional convolution operations with high bitwidth are used, then processing accuracy is maintained, but memory utilization deteriorates
Solution Approach 1:
The patent segments high-precision data into multiple low-precision bit representations. Instead of storing and processing full-precision floating-point numbers that consume significant memory, the method stores weights and activations as sequences of bits or small integer groups, dramatically reducing memory requirements. The segmentation allows accurate reconstruction of results through bitwise operations and popcount accumulation.
Solution Approach 2:
The patent changes the data representation parameter from high-bitwidth format (e.g., 32-bit or 64-bit floating-point) to low-bitwidth format (e.g., 1-bit, 2-bit, or 4-bit integers). This parameter change reduces the quantity of memory resources required to store kernel weights and activation maps while maintaining processing accuracy through proper bit-level computation and result aggregation using popcount operations.
3Use of energy by moving object
If bitwise operations are used, then energy consumption is reduced and memory utilization is improved, but computational complexity increases
Solution Approach 1:
The patent substitutes traditional mechanical arithmetic operations (multiplication and addition of floating-point numbers) with logical bitwise operations (AND, OR, XOR, popcount). These bitwise operations are natively supported by modern processors and can be executed more efficiently at the hardware level, reducing energy consumption despite the increased number of operational steps. The substitution leverages the parallel processing capability of bitwise logic to offset the apparent increase in computational complexity.
4Use of energy by moving object
If bitwise operations are used, then energy consumption is reduced, but the number of computational steps increases
Solution Approach 1:
The patent merges multiple traditional multiply-accumulate operations into a single bitwise operation sequence. By representing weights and activations in binary format, the method combines multiplication and addition into bitwise AND operations followed by popcount (population count) operations that count the number of set bits. This merging reduces the total number of high-energy arithmetic operations, and the increased step count is offset by the lower energy cost of each bitwise operation and the ability to execute multiple operations in parallel.
Data Source
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AI summary
A processor-implemented neural network processing method includes: obtaining a kernel bit-serial block corresponding to first data of a weight kernel of a layer in a neural network; generating a feature map bit-serial block based on second data of one or more input feature maps of the layer; and generating at least a portion of an output feature map by performing a convolution operation of the layer using a bitwise operation between the kernel bit-serial block and the feature map bit-serial block.