Bit-Serial Neural Network Computation with Dynamic Frequency Modulation
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Solution Overview
Problem
Conventional Dynamic Voltage Frequency Modulation (DVFM) techniques for bit-serial computation in neural networks are inefficient in terms of energy and delay, and fail to provide adequate error resiliency under noise conditions such as temperature variations and power fluctuations.
Innovation Solution
A computation system with a delay monitor and clock generator that dynamically adjusts the iteration-level processing duration threshold for bit-serial processing, prioritizing the Most Significant Bit (MSB) and skipping less significant bits if noise exceeds the remaining processing time, thereby ensuring error resiliency and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DVFM techniques are used to guarantee computation correctness under supply noise, then reliability is improved, but energy consumption and processing delay increase significantly
Solution Approach 1:
The patent implements dynamic frequency modulation where the clock frequency is adjusted in real-time based on detected computation errors. The system starts at a high frequency for speed, and upon detecting errors (indicating noise interference), dynamically lowers the frequency to guarantee correct computation, thus adapting the operating conditions to balance speed, energy, and reliability
Solution Approach 2:
The system changes the clock frequency parameter dynamically based on error detection results. By monitoring computation correctness and adjusting the frequency parameter accordingly, the system can operate at higher frequencies when conditions are good (saving energy) and lower frequencies when noise interference occurs (maintaining reliability)
2Reliability
If conventional DVFM techniques are used to guarantee computation correctness under supply noise, then reliability is improved, but processing delay increases significantly
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time error detection rather than using a conservative fixed low frequency throughout. This allows the system to maintain high processing speeds when noise interference is absent while only slowing down when actually needed to correct errors, thus reducing overall processing delay
Solution Approach 2:
The system performs error detection during the computation process and takes corrective action (frequency adjustment) only when errors are detected. This preliminary monitoring approach allows the system to complete most computations at high speed, intervening only when necessary to maintain correctness
3Manufacturing precision
If all bits are processed in bit-serial computation, then manufacturing precision is maintained, but processing time increases
Solution Approach 1:
The system processes bits in serial order from MSB to LSB, and when time constraints or errors are detected, it can skip processing less significant bits. This partial action approach maintains the most important precision (MSB) while sacrificing less critical bits to reduce overall processing time
Solution Approach 2:
The system applies different processing quality to different bits based on their significance. MSBs are processed with full accuracy and error checking, while LSBs may be skipped or processed with reduced precision when time or resource constraints exist, as they contribute less to overall computation accuracy
4Manufacturing precision
If processing duration threshold is increased to complete all iterations, then computation accuracy is improved, but energy consumption and delay increase
Solution Approach 1:
The system dynamically adjusts the processing duration threshold based on error detection and remaining computation requirements. Rather than using a fixed high threshold for all computations, the system adapts the threshold in real-time, extending it only when errors are detected and additional processing is needed to ensure correctness
Solution Approach 2:
The system changes the iteration-level processing duration threshold parameter dynamically based on the detected need for error correction. By monitoring computation progress and error rates, the system adjusts this parameter to achieve necessary accuracy while minimizing unnecessary energy consumption from extended processing
Data Source
AI summary
A system is provided for error resiliency in a bit serial computation. A delay monitor enforces an overall processing duration threshold for bit-serial processing all iterations for the bit serial computation, while determining a threshold for processing each iteration. At least some iterations correspond to a respective bit in an input bit sequence. A clock generator generates a clock signal for controlling a performance of the iterations. Each of iteration units perform a particular iteration, starting with a Most Significant Bit (MSB) of the input bit sequence and continuing in descending bit significant order, and by selectively increasing the threshold for at least one iteration while skipping from processing at least one subsequent iteration whose iteration-level processing duration exceeds a remaining amount of an overall processing duration for all iterations, responsive to the at least one iteration requiring more time to complete than a current value of the threshold.