Bit Shift Circuit for Memory Bandwidth Optimization
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Solution Overview
Problem
The limitation of memory bandwidth in computer applications, such as neural networks and machine learning, restricts execution speed, and existing solutions like high-bandwidth memory devices or data reduction techniques are costly and affect precision and processor load.
Innovation Solution
A memory device with a bit shift circuit that allows for shifting memory values within a row by connecting bit lines to sense amplifiers through semiconductor switch elements, enabling operations like multiplication or division by powers of two without burdening the memory interface, thus optimizing memory bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-bandwidth memory devices are used to address execution speed limitations, then memory bandwidth is improved, but device cost increases
Solution Approach 1:
The memory device performs arithmetic operations (multiplication/division by powers of two) using its own internal bit shift circuit rather than requiring external processor intervention. This self-service capability reduces the computational burden on external processors and optimizes memory bandwidth utilization, achieving faster execution without proportionally increasing device cost
Solution Approach 2:
The bit shift circuit is integrated into the memory device structure, allowing the same hardware to serve both as storage medium and as a processing unit for bit shifting operations. This multi-functionality eliminates the need for separate high-bandwidth memory devices while achieving improved execution speed for specific operations
2Productivity
If data reduction techniques like sparse matrices are used to reduce memory requirements, then memory bandwidth load is reduced, but manufacturing precision is worsened
Solution Approach 1:
The invention changes the parameter of data representation by using bit shift operations instead of full arithmetic operations. This parameter change allows efficient memory bandwidth utilization through compact data manipulation while preserving the full precision of the stored values, avoiding the precision loss associated with sparse matrix approximations
3Productivity
If numerical values with fewer significant digits are used to lower memory requirements, then memory bandwidth load is reduced, but measurement precision is worsened
Solution Approach 1:
The invention extracts only the essential operation (bit shifting) from complex arithmetic operations. By taking out and implementing only the bit shift functionality within the memory device, it reduces memory bandwidth requirements for complex calculations while maintaining full numerical precision, as the complete precision values remain stored in memory
4Productivity
If bit shift circuit is integrated into memory device to perform calculations directly, then execution speed is improved, but device complexity increases
Solution Approach 1:
The bit shift circuit is merged with the existing memory device structure, combining storage and processing functions in a single integrated unit. This merging approach achieves improved execution speed for bit shift operations while avoiding the complexity of completely separate processing units, as the circuit leverages existing memory infrastructure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances execution speed by reducing the load on memory bandwidth, lowers costs compared to high-bandwidth devices, and maintains precision while reducing processor load.
Implementation Method 1
each semiconductor switch element being connected to one of the bit lines and one of the sense amplifiers, so that in a conductive state of the semiconductor switch element an electrically conductive connection exists between the bit line and the sense amplifier
Data Source
AI summary
A memory device comprising a cell field having memory cells, N bit lines, which are respectively connected to at least one of the memory cells of the cell field, N being a whole number greater than one, N sense amplifiers; a bit shift circuit, which has S switch element rows, S being a whole number greater than one and a row number in the range from zero to S−1 being assignable to each switch element row. Each switch element row includes at least one semiconductor switch element connected to one of the bit lines and one of the sense amplifiers. Switch elements of each row connect all bit lines, whose bit line number is smaller than or equal to N minus the row number, to sense amplifiers, so that the respective sense amplifier number is equal to the respective bit line number plus the row number.