Latch-Flip-Flop Bit Shifter Layout for Smaller Digital Circuits

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Solution Overview

Problem

Conventional bit data shifters, relying on master-slave flip-flops, face limitations in reducing the layout area due to their inherent structure, which restricts the overall size reduction of digital circuits.

Innovation Solution

A bit data shifter is designed by combining single-stage latches and master-slave flip-flops in cascaded groups, where the latches delay input signals based on clock signals to generate delayed signals, and the master-slave flip-flop further delays these signals to feed the next group, effectively reducing the number of master-slave flip-flops and the layout area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the area of master-slave flip-flop is reduced to reduce the overall area of bit data shifter, then the layout area is reduced, but the area reduction is rather limited due to the main structure still being constituted of master-slave flip-flops

Engineering Contradiction:

Improvelayout area of bit data shifterVSAvoidstructure complexity of data shifter group

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The data shifter is segmented into multiple data shifter groups, where each group contains a mix of single-stage latches and master-slave flip-flops. This segmentation allows different types of storage elements to be distributed throughout the structure, reducing the overall area by replacing some master-slave flip-flops with more compact single-stage latches while maintaining the functional requirements of the data shifter.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different types of storage elements (single-stage latches and master-slave flip-flops) are used in different locations within the data shifter groups. The single-stage latches are placed in positions where full master-slave flip-flop functionality is not required, allowing for local area reduction while maintaining overall system performance.

Inventive Principle:

Principle #3Local quality

2Reliability

If more master-slave flip-flops are used to ensure reliable signal transmission, then the reliability is improved, but the layout area increases

Engineering Contradiction:

Improvesignal transmission reliabilityVSAvoidlayout area of bit data shifter

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges single-stage latches and master-slave flip-flops into hybrid data shifter groups. The single-stage latches provide compact signal transmission for certain stages, while master-slave flip-flops provide reliable edge-triggered transmission for critical stages. This combination achieves reliable signal transmission across the entire data shifter without requiring all elements to be full master-slave flip-flops, thus reducing the total area.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11177011B2Bit data shifter

Publication Date: 2021.11.16 WINBOND ELECTRONICS CORP

AI summary

A bit data shifter receives an input signal and a plurality of clock signals. The bit data shifter includes a plurality of data shifter groups cascaded in sequence, and each of the plurality of data shifter groups cascaded in sequence includes a plurality of data latches cascaded in sequence and a master-slave flip-flop. The plurality of data latches cascaded in sequence is configured to delay the input signal in sequence based on the plurality of clock signals to generate a plurality of delayed signals. The master-slave flip-flop is configured to delay one of the plurality of delayed signals based on one of the plurality of clock signals to generate an input signal of a next data shifter group.