Bit Slice Placement Regularity via Cell Swapping and Wiring Copying
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Solution Overview
Problem
Automated bit slice placement in semiconductor chip design often results in irregular arrangements, leading to unpredictable and suboptimal interconnect wiring, particularly for regular structures like multipliers and register files, which benefit from structured placement.
Innovation Solution
The proposed solution involves cell swapping, wiring copying, and cell duplication between bit slices to achieve regular and optimal placement, with flowcharts outlining the processes for identifying and aligning cells, checking Boolean equivalence, and improving the Quality of Result (QoR) to ensure functional consistency and reduced convoluted wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated placement is used for bit slices, then placement speed and productivity are improved, but placement regularity and wiring predictability deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-identifying bit slice structures and their constituent cells before the main placement process. The system prepares placement constraints and regularity requirements in advance, then guides the automated placer to respect these pre-established patterns, thereby maintaining placement regularity while achieving automation.
Solution Approach 2:
The patent applies local quality by implementing placement constraints specifically for bit slice cells rather than applying uniform placement rules across the entire chip. The system identifies regions containing bit slice cells and applies localized regularity constraints to these specific areas, allowing automated placement in other regions while maintaining structural regularity where needed.
2Adaptability or versatility
If random cell placement is used, then automation ease and adaptability are improved, but interconnect wiring regularity and timing predictability deteriorate
Solution Approach 1:
The patent applies feedback by implementing an iterative process that evaluates placement results against regularity constraints and timing requirements. The system monitors the placement of bit slice cells and adjusts subsequent placements to maintain wiring regularity, using feedback from timing analysis and routing congestion data to guide further placement decisions.
Solution Approach 2:
The patent applies dynamics by making placement constraints adaptive rather than fixed. The system dynamically adjusts placement regularity requirements based on the specific bit slice architecture, timing constraints, and routing considerations. Placement rules can be modified during the placement process to optimize both wiring regularity and timing performance.
3Reliability
If hand placement is used to achieve regular placement, then placement regularity and timing consistency are improved, but design time and complexity deteriorate
Solution Approach 1:
The patent applies copying by automatically replicating the placement patterns of reference bit slice cells to other identical or similar cells. Once a regular placement pattern is established for one bit slice, the system copies this pattern to other bit slices, maintaining timing consistency and wiring regularity without requiring manual placement of each cell individually.
Solution Approach 2:
The patent applies universality by creating a generalized placement methodology that can handle multiple types of bit slice structures (full adders, half adders, multiplexers, etc.) using a single automated framework. The system identifies universal patterns across different cell types and applies appropriate placement constraints, reducing the need for separate hand-placement procedures for each cell type.
Data Source
AI summary
Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.