Bit-Sliced CRC Circuit Using Galois-Field Arithmetic
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Solution Overview
Problem
Existing cyclic redundancy check (CRC) circuits are not scalable and efficient for arbitrary data lengths, particularly in storage and communication systems, and they do not effectively meet performance benchmarks for hardware-based storage I/O controllers.
Innovation Solution
A modular and expandable CRC circuit using Galois-field arithmetic, specifically employing a 16-bit CRC polynomial and a multiplier circuit with a GF2 modulo block, which calculates CRC results through bit-sliced processing and lookup tables, enabling high throughput and efficient error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional bit-serial LFSR methods are used for CRC calculation, then device complexity is reduced, but productivity is insufficient for high-performance storage I/O controllers
Solution Approach 1:
The patent divides the CRC calculation process into multiple parallel segments using bit-sliced architecture. Instead of processing bits sequentially, the circuit processes multiple bits simultaneously by dividing the LFSR into slices that operate in parallel, thereby increasing throughput while maintaining manageable complexity through modular design
Solution Approach 2:
The patent transitions from traditional time-serial bit processing to spatial parallelism by implementing bit-sliced LFSRs. This dimensional change allows multiple bit operations to occur simultaneously across different slices, dramatically improving productivity without proportionally increasing overall system complexity
2Adaptability or versatility
If traditional parallel methods with lookup tables are used, then productivity is improved, but adaptability to arbitrary data lengths is limited
Solution Approach 1:
The patent implements a dynamic architecture where the number of LFSR slices and their configuration can be adjusted based on the input data length and CRC polynomial requirements. This dynamic adaptability allows the same circuit to efficiently handle various data lengths and CRC variants without requiring complete redesign or large static lookup tables
Solution Approach 2:
The bit-sliced LFSR design provides universal functionality that can compute CRC for any data length and polynomial by configuring the appropriate number of slices and feedback connections. This multi-functional capability replaces the need for multiple dedicated circuits or large lookup tables, achieving adaptability with controlled complexity
3Productivity
If CRC circuit is designed for specific data lengths, then manufacturing precision is improved, but adaptability to various data lengths deteriorates
Solution Approach 1:
By segmenting the LFSR into configurable slices, the patent enables the circuit to be tailored for specific data lengths and CRC polynomials when needed, while maintaining the flexibility to reconfigure for different requirements. Each slice can be independently configured, allowing optimization for specific applications while preserving overall adaptability
Data Source
AI summary
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.