Bit-Sliced Multiply-Accumulate Memory Layout Without DAC Overhead
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiply-accumulate operations in Deep Neural Networks (DNNs) face challenges in energy efficiency, area overhead, and reliability due to the need for DAC circuits and simultaneous driving of word lines, especially when using multi-value bit inputs, which can degrade recognition accuracy.
Innovation Solution
A multiply-accumulate operation device with memory blocks that store data of the same bit digit of multiplied elements, using A/D converters and a control unit to efficiently perform multiply-accumulate operations by dividing data into bit digits and storing them in separate memory blocks, reducing the need for DACs and minimizing redundant data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-value bit input is used to improve recognition accuracy, then recognition accuracy is improved, but memory size must be increased
Solution Approach 1:
The patent segments the multiplication elements into multiple groups, where each group contains elements with the same bit digit position. These groups are stored in separate memory blocks, allowing multi-value bit input operations without requiring a single large memory array. The segmentation enables efficient storage and processing of multi-bit data while maintaining compact memory structure.
Solution Approach 2:
The patent introduces a new dimension of organization by grouping multiplication elements according to their bit digit positions rather than storing them in a traditional flat array. This dimensional reorganization allows the system to handle multi-value bit inputs by accessing specific bit digit groups across multiple memory blocks, effectively increasing precision without proportionally increasing memory size.
2Adaptability or versatility
If DAC circuit is provided at input portion to enable multi-value bit input, then multi-value bit input operation is enabled, but energy consumption increases
Solution Approach 1:
The patent extracts the DAC circuit functionality from the input portion and eliminates the need for external DAC circuits by implementing multi-value bit input directly within the memory array structure. The memory blocks store multiplication elements organized by bit digit positions, allowing direct digital access to multi-value inputs without requiring analog-to-digital conversion hardware, thereby reducing energy consumption.
Solution Approach 2:
The memory array itself provides the functionality that would otherwise require external DAC circuits. By organizing multiplication elements into groups based on bit digit positions and enabling direct digital access to these groups, the system makes the memory structure self-sufficient for multi-value bit input operations, eliminating the need for separate DAC hardware and associated energy consumption.
3Productivity
If DAC circuit is provided for each column to perform multiply-accumulate operation, then multiply-accumulate operation is enabled, but area overhead increases
Solution Approach 1:
The patent merges the functionality of multiple DAC circuits into a single unified memory block structure. Instead of having separate DAC circuits for each column, the system uses a single memory block that stores multiplication elements organized by bit digit positions, allowing the entire array to function as an integrated unit for multiply-accumulate operations without requiring redundant DAC hardware in each column.
Solution Approach 2:
The memory block structure serves multiple functions simultaneously: it stores multiplication elements, organizes them by bit digit positions, and provides direct digital access for multi-value bit input operations. This universal design eliminates the need for separate DAC circuits in each column, reducing area overhead while maintaining full multiply-accumulate operation capability.
4Productivity
If large number of word lines are driven simultaneously to perform multiply-accumulate operation, then multiply-accumulate operation is enabled, but energy consumption increases
Solution Approach 1:
The patent segments the word lines into groups corresponding to different bit digit positions. Instead of driving all word lines simultaneously, the system activates only the word lines associated with the current bit digit being processed. This segmentation enables parallel processing across different bit positions while significantly reducing the total number of word lines driven at any given time, thereby lowering energy consumption.
Solution Approach 2:
The patent implements periodic activation of word lines based on the bit digit position being processed. Word lines are driven in sequential periods corresponding to different bit digits (0th bit, 1st bit, 2nd bit, etc.), allowing the system to complete multiply-accumulate operations through multiple periodic cycles. This periodic action enables high throughput while reducing peak energy consumption by avoiding simultaneous activation of all word lines.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A multiply-accumulate calculation device, a multiply-accumulate calculation method, and a system for efficiently performing a multiply-accumulate calculation are provided. The multiply-accumulate operation device includes a plurality of memory blocks that store a plurality of multiplied elements and performs a multiply-accumulate operation on input data. Each of memory blocks includes stores one bit value of the same bit digit of a plurality of multiplied elements. An input data generation unit generates input data by extracting data of a same bit digit from the plurality of multiplication elements. A control unit that accumulates and adds value of the multiply-accumulate operation result, and a data memory that stores the accumulated addition value as a multiplication element of the next multiply-accumulate operation.