Memory Control Circuit for Bit-Specific Sensing Margins
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Solution Overview
Problem
Conventional memory systems do not optimize sensing margin allocation for neural network and computing-in-memory (CiM) operations, leading to inefficiencies and increased bit error rates.
Innovation Solution
A control circuit that programs memory cells based on error tolerance of each bit, reducing overlapping areas in electrical characteristic distributions to minimize bit error rates by adjusting voltage levels and bit line configurations for precise data storage and computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If equal sensing margin is allocated to each bit in conventional memory systems, then the system maintains simple and uniform control, but the bit error rate increases and computational accuracy deteriorates for neural network and CiM operations
Solution Approach 1:
The patent applies local quality by allocating different sensing margins to different bits based on their individual error tolerances. The control circuit identifies which bits have higher error tolerance and allocates larger sensing margins to those bits, while maintaining smaller margins for bits with lower tolerance. This non-uniform allocation optimizes reliability for neural network and CiM operations without requiring complete redesign of the control system.
Solution Approach 2:
The patent changes the sensing margin parameter from a fixed equal value to variable values based on bit-specific error tolerance characteristics. The control circuit dynamically adjusts sensing margin parameters for different bits during read operations, allowing the system to adapt to the varying reliability requirements of different bit positions in neural network weight data.
2Measurement precision
If conventional equal sensing margin allocation is used, then the control system remains simple, but computational accuracy for neural network operations deteriorates
Solution Approach 1:
The control circuit implements local quality by applying different sensing margin values to different bits based on their error tolerance. This allows the system to achieve higher computational accuracy for neural network operations by prioritizing sensing resources for bits that contribute more significantly to computation accuracy, while accepting larger margins for less critical bits.
3Reliability
If uniform sensing margin is applied to all bits, then the memory system operates with consistent control parameters, but robustness against silicon imperfections and noise decreases
Solution Approach 1:
The patent applies local quality by tailoring sensing margin allocation to the specific error tolerance characteristics of each bit position. The control circuit identifies bits that are more susceptible to silicon imperfections and noise and allocates larger sensing margins to those bits, thereby enhancing robustness against imperfections in a targeted manner rather than uniformly across all bits.
Data Source
AI summary
A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.