Bit Spreading Memory Verification for Radiation Error Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems in space-based applications are prone to radiation-induced errors, such as single-bit, multi-bit, and SEFI errors, which can corrupt data and render memory non-functional. Existing solutions like shielding and redundant memories with majority voting techniques are either impractical due to weight constraints or increase cost and complexity.
Innovation Solution
A bit spreading memory system that distributes data bits and associated ECC codes across multiple RAMs, reducing radiation-induced error susceptibility by spreading the data over multiple memory units. A design verification process using a bit spreading geometry file is employed to ensure correct implementation of the bit spreading technique.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shielding is used to reduce radiation exposure, then radiation-induced error rates are reduced, but weight increases due to lead or similarly dense materials
Solution Approach 1:
The memory system is divided into multiple independent RAM units, each storing a portion of the data bits. This segmentation allows the system to distribute radiation exposure across multiple smaller units rather than protecting a single large memory block, reducing the weight penalty of shielding while maintaining error resistance through spatial distribution of data bits across separate physical locations
Solution Approach 2:
Error correction codes serve as an intermediary mechanism that detects and corrects radiation-induced errors without requiring physical shielding. The ECC system mediates between the radiation environment and the memory data, providing error protection through computational correction rather than physical barriers, thereby avoiding the weight increase associated with dense shielding materials
2Reliability
If redundant memories with majority voting techniques are used, then error rates are reduced, but cost and complexity increase
Solution Approach 1:
The data is segmented into multiple bits distributed across different RAM units, with each bit independently stored in separate physical locations. This segmentation enables the system to tolerate errors in individual bits or RAM units without requiring complex redundant memory structures, as the distributed architecture naturally provides error isolation and recovery capabilities through the bit spreading code
Solution Approach 2:
The system changes the parameter of data representation by using bit spreading codes that map logical data bits to multiple physical bit positions across different RAM units. This parameter transformation allows the memory system to achieve error resistance through the mathematical properties of the spreading code rather than through redundant hardware copies, thereby reducing complexity compared to traditional majority voting schemes that require multiple identical memory units
Data Source
AI summary
Techniques are provided for design verification of a bit spreading memory. A methodology implementing the techniques according to an embodiment includes using a bit spreading geometry file to convert a logical address of the memory to a physical address. The geometry file defines a scheme by which bits of a data word stored at the logical address are spread over multiple RAMs. The method also includes writing data bits of a test data word to the physical address, causing a design simulator to simulate a read from the logical address, and comparing the result to the test data word for verification. The method further includes causing the design simulator to simulate a write of the test data word to the logical address, reading data bits from the physical address, arranging the bits into a retrieved data word, and comparing the test data word to the retrieved data word for verification.