Bit Steering Logic for Serial Link Lane Speed Optimization

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Solution Overview

Problem

Existing serial communication links face inefficiencies in data transmission due to variations in bit error rates (BER) across lanes, leading to suboptimal throughput and reliability, as they lack adaptive mechanisms to dynamically adjust lane speeds and participation based on real-time performance.

Innovation Solution

Implementing bit steering logic that dynamically adjusts the proportion of data bits across multiple lanes operating at different speeds, reconfiguring lane participation and speed settings based on current bit error rates to maintain desired BER and maximize throughput, using encoding and decoding schemes to ensure error detection and correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If all lanes operate at the highest speed, then throughput is maximized, but bit error rate increases due to channel variations

Engineering Contradiction:

ImprovethroughputVSAvoidbit error rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by allowing different lanes to operate at different speeds based on their individual performance characteristics. The bit steering logic dynamically assigns bits to lanes according to their current quality state, so that lanes with better signal quality can transmit at higher speeds while lanes with poorer quality operate at lower speeds, thereby optimizing both throughput and reliability simultaneously

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system implements dynamics through the bit steering logic that continuously monitors lane performance and dynamically adjusts lane participation and speed allocation in real-time. This dynamic adaptation allows the system to respond to changing channel conditions, maintaining optimal throughput while preventing error rates from exceeding acceptable thresholds

Inventive Principle:

Principle #15Dynamics

2Productivity

If lanes are operated at different speeds, then link performance is optimized, but device complexity increases due to bit steering logic

Engineering Contradiction:

Improvelink performanceVSAvoidbit steering logic

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The bit steering logic is designed with multi-functionality, serving as a universal control mechanism that handles both speed allocation and lane selection functions. This consolidates multiple control tasks into a single integrated component, reducing overall system complexity while enabling sophisticated lane management

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system manages complexity by dynamically changing operational parameters (lane speed assignments and bit distribution ratios) rather than requiring complex hardware reconfiguration. This software-defined approach allows flexible optimization through parameter adjustment without proportionally increasing hardware complexity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9825730B1System and method for optimizing link performance with lanes operating at different speeds

Publication Date: 2017.11.21 DELL PROD LP

AI summary

A serial communication link includes a receiver and a transmitter coupled to the receiver by a first serial communication lane operating at a first speed, and a second serial communication lane operating at a second speed. The second speed is slower than the first speed. The transmitter can include bit steering logic that receives a data stream, provides a first number of bits of the data stream to the first serial communication lane, and provides a second number of bits to the second serial communication lane. The proportion of the first number of bits to the second number of bits is the same as a proportion of the first speed to the second speed.