Bit Stream Processing Device for Pipe-lined Decoding
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Solution Overview
Problem
Mobile devices face challenges in processing large multimedia data due to limited bandwidth and storage capacity, particularly when using flexible macroblock ordering (FMO) for video data, which can degrade decoding speed if continuity of macroblocks is not secured.
Innovation Solution
A bit stream processing device with a virtual division memory, stream shift buffer, and controller that performs pipe-lined decoding by dividing memory into group regions, managing write and read operations, and storing backup states to maintain decoding speed during transitions between stream groups, allowing for efficient decoding in raster-scan order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flexible macroblock ordering (FMO) is used to enhance compression rate and image quality, then compression efficiency is improved, but decoding speed is degraded due to loss of macroblock continuity
Solution Approach 1:
The memory is divided into multiple group memory regions, each corresponding to a specific stream group. This segmentation allows the decoder to efficiently manage and access different stream groups independently, facilitating the switching between FMO and raster-scan decoding modes without compromising decoding speed or continuity.
Solution Approach 2:
The system performs preliminary organization of bit streams into distinct stream groups and allocates corresponding group memory regions in advance. This preliminary action enables the decoder to quickly switch between different decoding modes by simply changing the read pointer target, without requiring complex real-time reorganization during decoding, thus maintaining high decoding speed.
2Productivity
If FMO is used to rearrange macroblocks in flexible order, then compression efficiency is improved, but continuity of decoded macroblocks is lost
Solution Approach 1:
The system dynamically switches between two decoding modes: FMO mode for compression efficiency and raster-scan mode for macroblock continuity. The controller selectively activates the appropriate mode based on the decoding requirements, allowing the system to adapt its behavior to maintain both compression efficiency and macroblock continuity as needed.
Solution Approach 2:
The system changes the decoding parameter (decoding order) based on the stream group being processed. By controlling the read pointer to output data in either FMO order or raster-scan order, the system adjusts the macroblock output sequence parameter to match the required continuity, thereby resolving the contradiction between flexible ordering and continuity.
3Speed
If pipe-lined decoding is implemented to maintain decoding speed, then decoding continuity is improved, but device complexity increases due to additional memory structures and control mechanisms
Solution Approach 1:
The group memory regions serve multiple functions: they store bit streams for different stream groups, act as buffer memory for pipe-lined decoding, and provide structured access paths for both FMO and raster-scan modes. This multi-functionality reduces the need for separate dedicated memory structures, thereby limiting the increase in device complexity while enabling pipe-lined decoding.
Data Source
AI summary
A bit stream processing device may include a virtual division memory, a stream shift buffer, a decoder circuit, and a controller. The virtual division memory may be divided into a plurality of group memory regions configured to store a plurality of stream groups in the respective group memory regions and to output a memory bit stream. The stream groups may be included in an input bit stream. The stream shift buffer is configured to receive and store the memory bit stream and output a buffer bit stream. The decoder circuit is configured to perform a decoding operation on the buffer bit stream from the stream shift buffer. The controller is configured to control operations of the virtual division memory, the stream shift buffer, and the decoder circuit.