Bit Stream Encoding with Flag Bits for Timing Recovery

The patent applies preliminary action by inserting flag bits into the bit stream before transmission to prevent potential errors. The flag bits are placed in advance at positions that may indicate consecutive zeros or ones, allowing the receiver to maintain correct timing without waiting for errors to occur. This proactive approach improves reliability while adding only minimal encoding complexity.

The flag bit serves as an intermediary element between the transmitter and receiver. It provides timing reference information that mediates the synchronization between the two ends, especially when consecutive identical bits cause phase shift or frequency deviation. This intermediary mechanism resolves the contradiction by improving reliability through timing recovery without requiring complex encoding schemes.

The patent applies local quality by inserting flag bits only at specific local positions in the bit stream where consecutive zeros or ones are detected, rather than uniformly throughout the entire stream. This localized approach maintains reliability by targeting error-prone areas while keeping the overall encoding implementation relatively simple, as not all positions require flag bit insertion.

The patent changes the parameter of bit stream structure by inserting additional flag bit elements at specific positions. This parameter change (adding selective bits) improves reliability by enabling better timing recovery, while the simplicity of the implementation is maintained through straightforward detection and insertion logic based on consecutive bit patterns.

The patent applies partial action by inserting flag bits only when and where needed (at positions with consecutive zeros or ones), rather than adding flag bits to every position in the bit stream. This partial approach improves timing recovery precision at error-prone locations while minimizing the overall impact on data transmission efficiency, as most positions do not require additional flag bits.

By inserting flag bits preliminarily at detected consecutive bit positions, the patent enables accurate timing recovery without continuously extending the bit stream. The preliminary insertion at specific locations provides sufficient timing reference information to maintain precision while avoiding the excessive overhead that would result from universal flag bit insertion, thus preserving transmission efficiency.