Bit Swap Encoding for Flash Memory Programming Optimization

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Solution Overview

Problem

The high programming costs associated with MultiLevel Cell (MLC) technology in flash memories, which store multiple bits per memory cell, necessitate a solution to manage these costs effectively.

Innovation Solution

Implementing a bit swap encoding method that identifies dominant bit pair combinations in memory regions and swaps them with the 'do-nothing' erased level, optimizing programming times and reducing system power consumption by minimizing the number of cells that need to be programmed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC technology is used to store multiple bits per memory cell, then storage density is improved, but programming cost and complexity increase

Engineering Contradiction:
Improvestorage densityVSAvoidprogramming complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by transforming the bit representation from standard binary (0-3 for 2 bits per cell) to a modified encoding scheme where the most significant bit is inverted and mapped to a special erased state. This changes the parameter space from {0,1,2,3} to {E,0,1,2} where E represents the erased state, enabling the memory controller to distinguish between programmed and unprogrammed cells more efficiently, thereby reducing programming complexity while maintaining high storage density

Inventive Principle:
Principle #35Parameter changes

2Productivity

If bit swap encoding is applied to optimize programming, then programming efficiency is improved, but encoding complexity increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidencoding complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by having the memory controller pre-calculate and prepare the bit swap encoding mappings before actual programming operations occur. The controller maintains lookup tables that define the correspondence between original bit values and their swapped equivalents based on the dominant bit pattern analysis performed in advance. This preliminary preparation eliminates the need for complex real-time encoding calculations during programming, thereby improving productivity while keeping the actual encoding implementation simple

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs feedback mechanisms where the memory controller continuously monitors the programming results and uses this information to determine the dominant bit pattern in each memory region. Based on this feedback, the controller dynamically adjusts the bit swap encoding strategy for different regions, optimizing programming efficiency for each specific case while maintaining a relatively simple overall encoding implementation through adaptive rather than predetermined complex rules

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7644225B2Performance or power-optimized code/data storage for nonvolatile memories
Publication Date: 2010.01.05 INTEL NDTM US LLC
  • US7644225B2 patent drawing
  • US7644225B2 patent drawing
  • US7644225B2 patent drawing

AI summary

A wireless device incorporates a nonvolatile memory that dynamically controls a swapping or mapping of bit pairs for a selected memory region to optimize programming times.