Bit-Swapped Parallel-Serial Conversion for Variable Data Widths
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Solution Overview
Problem
Existing parallel to serial conversion apparatuses face challenges in converting input parallel data of varying widths without compromising high-speed operation, as they require complex circuitry and fixed conversion ratios, making it difficult to select the width of input parallel data.
Innovation Solution
Incorporating a bit-swapping circuit that rearranges input parallel data and a parallel to serial conversion circuit with a tree-type structure, allowing for the conversion of parallel data with selectable widths by generating bit-swapped data and arranging bits in different orders based on a mode-setting signal, enabling flexible conversion without losing high-speed operation capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a tree-type parallel to serial conversion circuit is used for high-speed operation, then operation speed is improved, but the conversion ratio is fixed to 2^n and cannot be changed
Solution Approach 1:
The patent applies dynamics by making the conversion ratio adjustable rather than fixed. The control signal dynamically selects between different conversion ratios (e.g., 2:1, 4:1, 8:1), allowing the system to adapt its behavior based on operational requirements while maintaining the tree-type structure for high-speed performance.
Solution Approach 2:
The patent changes the parameter of conversion ratio from a fixed value to a variable parameter controlled by control signals. By varying the conversion ratio parameter based on input data width requirements, the system achieves both high-speed operation and flexibility in handling different data widths.
2Adaptability or versatility
If the width of input parallel data is selected to be variable, then adaptability is improved, but circuit complexity increases
Solution Approach 1:
The patent achieves universality by designing a single tree-type conversion circuit that can handle multiple data widths (e.g., 2-bit, 4-bit, 8-bit parallel data) through configurable conversion ratios. This multi-functional approach eliminates the need for separate conversion circuits for each data width, thereby reducing overall circuit complexity while maintaining adaptability.
3Speed
If high-speed shift registers are used for wide parallel data conversion, then conversion speed is improved, but layout design becomes difficult and power consumption increases
Solution Approach 1:
The patent segments the parallel to serial conversion process into multiple stages of 2:1 multiplexer operations within the tree-type structure. This segmentation allows high-speed operation to be achieved through multiple simple stages rather than a single complex high-speed shift register, making layout design easier and reducing power consumption while maintaining conversion speed.
Data Source
AI summary
Various exemplary embodiments of this disclosure provide parallel to serial conversion apparatuses that includes a bit-swapping circuit that generates bit-swapped parallel data by swapping bits of input parallel data, and a parallel to serial conversion circuit that acquires M1 and M2 bits of the bit-swapped parallel data in a first and a second mode, respectively. The parallel to serial conversion circuit generates serial data by arranging the acquired bits of the bit-swapped parallel data in a first specified order in the first mode and in a second specified order in the second mode The bit-swapping circuit swaps the bits of the input parallel data such that the parallel to serial conversion circuit acquires 1st to M1-th and 1st to M2-th bits of the input parallel data in the first and second modes, respectively, and arranges the acquired bits of the input parallel data in the same order.