Bit Tagging for Non-Volatile Memory Decoding Efficiency

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Solution Overview

Problem

Consecutive execution of hard bit mode and soft bit mode decoding operations in rewritable non-volatile memory modules results in low accessing efficiency due to the independence of these operations, where soft bit mode decoding lacks information from hard bit mode decoding.

Innovation Solution

A bit tagging method that learns the position of unreliable bits in hard bit mode decoding and obtains related information (decoding initial values) to apply in soft bit mode decoding, improving the accessing efficiency of the rewritable non-volatile memory module by adjusting decoding initial values based on differences between codewords obtained at varying reading voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hard bit mode decoding operation and soft bit mode decoding operation are consecutively executed independently, then decoding can be performed, but accessing efficiency of the rewritable non-volatile memory module is low

Engineering Contradiction:
Improveaccessing efficiencyVSAvoidinformation loss between decoding operations
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent merges the hard bit mode decoding operation and soft bit mode decoding operation into a unified decoding process. The hard bit mode decoding results are integrated into the soft bit mode decoding as initial values or priors, allowing the soft bit mode to leverage information from the hard bit mode rather than starting independently. This combination eliminates the information loss that occurs when operations are executed independently and consecutively.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The hard bit mode decoding operation is executed first as a preliminary action to obtain initial decoding results. These results are then used as starting points or priors for the soft bit mode decoding operation. By performing the hard bit mode decoding beforehand and incorporating its results into the subsequent soft bit mode decoding, the system prepares valuable information in advance that improves the efficiency of the overall decoding process.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If soft bit mode decoding operation does not refer to hard bit mode decoding information, then decoding operations remain independent and simple, but accessing efficiency decreases

Engineering Contradiction:
Improveaccessing efficiencyVSAvoiddecoding operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The hard bit mode decoding is performed as a preliminary action before the soft bit mode decoding. The results from the hard bit mode (such as decoded bits or reliability information) are prepared in advance and then fed into the soft bit mode decoding as initial values or priors. This preliminary action approach allows the soft bit mode to start with valuable information already processed, improving efficiency without requiring complex real-time interactions between the two decoding modes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10522234B2Bit tagging method, memory control circuit unit and memory storage device
Publication Date: 2019.12.31 PHISON ELECTRONICS
  • US10522234B2 patent drawing
  • US10522234B2 patent drawing
  • US10522234B2 patent drawing

AI summary

A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.