Bit Transposition Circuit for Secure Memory Access

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Solution Overview

Problem

Existing data security schemes are vulnerable to attacks through data and address buses during memory access operations, as sensitive information such as cryptographic keys is stored externally, providing an access point for unauthorized access.

Innovation Solution

A secure data transfer circuit that transposes bits in control values using a programmable switching circuit, generating a random internal mapping to scramble data and address bits during memory access operations, ensuring secure data transfer between a processor and memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored externally in memory during memory access operations, then data storage capacity is improved, but data security deteriorates due to vulnerability through data and address buses

Engineering Contradiction:
Improvedata storage capacityVSAvoiddata security vulnerability
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a secure data transfer circuit as an intermediary component between the processor and external memory. This circuit includes a programmable switching circuit that randomly interconnects bus lines to transpose bits in control values during memory access operations. The transposition creates an obscured representation of actual data and addresses on the buses, preventing unauthorized access while maintaining normal memory storage and access functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If bits in control values are transposed using a programmable switching circuit, then data security is improved, but device complexity increases

Engineering Contradiction:
Improvedata securityVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent changes the parameter of bit arrangement in control values by using a programmable switching circuit to randomly interconnect bus lines. This transposition alters the positional parameters of bits without changing their fundamental nature or requiring complex cryptographic processing. The programmable switch allows flexible configuration of transposition patterns while maintaining hardware efficiency.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If a programmable switching circuit is used to randomly interconnect bus lines, then entropy is increased for security, but ease of operation deteriorates

Engineering Contradiction:
Improvesecurity entropyVSAvoidoperation simplicity
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The secure data transfer circuit operates autonomously to perform bit transposition during memory access operations. The programmable switching circuit automatically randomizes the interconnection of bus lines based on stored transposition patterns, eliminating the need for manual configuration or complex control logic. The system self-manages the security function while maintaining normal processor operations.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11017128B2Data security using bit transposition during memory accesses
Publication Date: 2021.05.25 SEAGATE TECH LLC
  • US11017128B2 patent drawing
  • US11017128B2 patent drawing
  • US11017128B2 patent drawing

AI summary

Apparatus and method for transferring data between a processing circuit and a memory. In some embodiments, a data storage device has a main non-volatile memory (NVM) configured to store user data from a host device. A controller circuit is configured to direct transfers of the user data between the NVM and the host device. The controller circuit has a programmable processor and a secure data transfer circuit. The secure data transfer circuit executes memory access operations to transfer user data and control values between the processor and a local memory. A memory access operation includes receiving bits of a multi-bit control value on a multi-line bus from the processor, and activating a programmable switching circuit to randomly interconnect different ones of the multi-line bus to transpose the bits in the control value.