Bit Vector Operation Device Direct Data Transfer

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Solution Overview

Problem

Existing memory systems face inefficiencies in data transfer between processing resources and memory arrays, often requiring intermediate copies of data through operating system caches, which slows down data transfer rates.

Innovation Solution

The implementation of a bit vector operation device coupled with a data transform engine (DTE) allows for direct data transfer between memory devices, including processing in memory (PIM) devices, by rearranging data using indicators or flags within data packets, thus bypassing the need for intermediate copies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transferred through operating system caches between processing resources and memory arrays, then data transfer can be performed with existing memory systems, but data transfer rates are slowed down due to intermediate copies

Engineering Contradiction:

Improvedata transfer rateVSAvoiddata transfer path complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the intermediate operating system cache from the data transfer path between processing resources and memory arrays. By implementing direct data transfer mechanisms that bypass the traditional cache architecture, the system removes the bottleneck that caused intermediate copies and slowed down data transfer rates.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a new intermediary mechanism - a direct data transfer interface or protocol - that enables communication between processing resources and memory arrays without requiring the traditional operating system cache. This new intermediary provides a more efficient data transfer path while maintaining system compatibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If intermediate copies of data are made through operating system caches, then data can be buffered and sequenced, but system performance deteriorates due to additional transfer steps

Engineering Contradiction:

Improvesystem performanceVSAvoiddata transfer time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary data preparation and organization functions directly at the memory array or in dedicated data transfer hardware, eliminating the need for intermediate buffering and sequencing operations in the operating system cache. Data is prepared in advance in the optimal format for processing, reducing subsequent transfer time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent establishes a continuous data transfer pipeline between memory arrays and processing resources, eliminating the start-stop nature of traditional cache-based transfers. Data flows continuously through the direct transfer path without being halted for intermediate storage and retrieval operations, maintaining productive action throughout the transfer process.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250156440A1Data transfer with a bit vector operation device

Publication Date: 2025.05.15 LODESTAR LICENSING GROUP LLC

AI summary

Examples of the present disclosure provide apparatuses and methods for direct data transfer. An example method comprises transferring data between a first device and a second device, wherein the first device is a bit vector operation device, and transforming the data using a data transform engine (DTE) by rearranging the data to enable the data to be stored on the first device when transferring the data between the second device and first memory device.