Bitcell Wordline Strapping Circuitry for Area Reduction

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Solution Overview

Problem

In advanced process nodes, bitcells in standard cell libraries face compromised performance due to higher poly-silicon resistance, leading to increased area requirements in wide bitcell arrays, which is undesirable in modern miniaturized circuitry.

Innovation Solution

The implementation of bitcell wordline strapping circuitry within the bitcell itself, using a wordline strap to couple the bitcell to a metal wire, reduces resistance and area by eliminating the need for an extra bitcell to tap the metal wire, thereby optimizing power, performance, and area (PPA) in ROM bitcells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an extra bitcell is used to tap the metal wire with poly-silicon, then the wordline strapping is achieved, but the area increases drastically

Engineering Contradiction:

Improvewordline strappingVSAvoidbitcell array area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the wordline strapping function with the existing bitcell structure by integrating the strap within the bitcell boundaries. This combines multiple functions (storage and wordline tapping) into a single unified structure, eliminating the need for separate extra bitcells and reducing overall array area while maintaining strapping reliability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The bitcell is designed to serve multiple functions: it acts as both a storage element and a wordline tap point. By making the bitcell universal and multi-functional, the patent eliminates the need for dedicated extra bitcells for strapping, thereby reducing area while achieving the required wordline tapping capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If poly-silicon resistance is higher than metal resistance, then the wordline performance is compromised, but using metal wire in parallel increases area

Engineering Contradiction:

Improvewordline performanceVSAvoidbitcell array area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by using metal material specifically for the wordline strap portion within the bitcell where low resistance is critical, while maintaining poly-silicon for the main wordline. This localized use of metal with superior electrical properties improves wordline performance at the critical interface without requiring extensive metal wiring throughout the array

Inventive Principle:

Principle #3Local quality

3Reliability

If tap-strapping frequency is increased, then the wordline coverage is improved, but the area increases with the increase in tapping frequency

Engineering Contradiction:

Improvewordline coverageVSAvoidbitcell array area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10923161B2Bitcell wordline strapping circuitry

Publication Date: 2021.02.16 ARM LTD

AI summary

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.