Bitlane-Specific ECC Symbols for Memory Error Correction
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Solution Overview
Problem
Existing memory subsystems face limitations in fault detection and correction, particularly in narrow parallel interfaces where errors are not effectively isolated to specific memory chips or bus wires due to the delivery of ECC words in packets over multiple cycles.
Innovation Solution
A memory subsystem with a memory bus and assembly that utilizes ECC symbols associated with each bitlane, allowing for error detection and correction by receiving and transmitting ECC words in multiple packets, and employing a symbol-oriented ECC scheme that corrects single and double symbol errors, while reducing the number of ECC bitlanes and pins required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC words are delivered in packets over multiple cycles in narrow parallel interfaces, then data transmission is achieved, but error isolation to specific memory chips or bus wires is not effective
Solution Approach 1:
The patent segments the ECC protection scope from the entire packet to individual bitlanes. Each bitlane has its own ECC symbols that protect only the data bits transmitted over that specific bitlane, enabling precise error localization to the faulty bitlane while maintaining reliable error correction capability.
Solution Approach 2:
The patent introduces bitlane-specific ECC symbols as intermediaries between the data bits and the error correction process. These ECC symbols act as mediators that are exclusively responsible for detecting and correcting errors in their associated bitlane, enabling precise error isolation.
2Productivity
If traditional ECC schemes are used with packetized delivery over multiple cycles, then data transmission is achieved, but the number of ECC bitlanes and pins required is large
Solution Approach 1:
The patent divides the ECC protection into separate segments for each bitlane, allowing independent error correction for each bitlane. This segmentation enables more efficient utilization of ECC bits and reduces the total number of ECC bitlanes and pins required compared to traditional packet-level ECC schemes.
Solution Approach 2:
The patent transitions from protecting data in the time dimension (across multiple cycles) to protecting data in the spatial dimension (across bitlanes). Each bitlane has its own ECC symbols, creating a spatial organization of error protection that reduces the overall system complexity.
3Productivity
If higher data rates are supported, then productivity is improved, but error detection and correction robustness may be compromised
Solution Approach 1:
By segmenting ECC protection to the bitlane level, the patent enables independent error correction for each bitlane regardless of the overall data rate. This allows the system to maintain robust error handling even at higher data rates where errors may occur more frequently.
Solution Approach 2:
The patent changes the organizational parameter of ECC from packet-level to bitlane-level, and supports configurable symbol sizes (e.g., 4-bit, 8-bit symbols). This parameter flexibility allows optimization of error correction robustness for different data rate requirements.
Data Source
AI summary
A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.