Bitline Boost Circuit for Fast Settling in CMOS Image Sensors
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Solution Overview
Problem
CMOS image sensors face challenges with fixed pattern noise (FPN) and slow bitline settling times due to RC delay, leading to image degradation and performance issues under varying lighting conditions, especially in high dynamic range applications.
Innovation Solution
The proposed solution involves a pixel output circuit with a bitline enable transistor, cascode and bias current source generators, and a blacksun voltage generator to control bitline voltage and current, allowing for fast settling by pre-charging the bitline with an idle voltage generator and using a clamp voltage generator to maintain stable power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a clamp voltage generator is used to limit bitline voltage swing, then FPN is reduced under high lighting conditions, but large current variation occurs to the power supply
Solution Approach 1:
The patent introduces a current source generator as an intermediary component between the bitline and the clamp voltage generator. This current source acts as a mediator that provides a stable current reference, preventing large current variations to the power supply while still allowing the clamp voltage generator to effectively limit bitline voltage swing and reduce FPN.
Solution Approach 2:
The patent employs an adjustable bias current source that can dynamically change its current parameter based on operating conditions. By adjusting the bias current, the system can maintain stable power supply current while adapting to different lighting conditions, thus reducing FPN without causing large power supply current variations.
2Loss of time
If the pixel cell is disconnected from the bitline during charge transfer, then settling time is reduced, but the bitline requires reconnection and additional control circuitry
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitline to a specific voltage level before the charge transfer operation. The idle voltage generator prepares the bitline in advance, so when the pixel cell reconnects to the bitline, the voltage difference is minimized, resulting in faster settling time without requiring complex disconnection control circuitry.
Solution Approach 2:
The system uses the existing bitline enable transistor and voltage generation circuits to automatically manage the bitline state. The idle voltage generator and clamp voltage generator work together with the bitline enable transistor to self-regulate the bitline voltage, eliminating the need for additional complex control circuitry while achieving fast settling.
3Loss of time
If the bitline is charged by pull-up current through SF transistor under dark condition, then settling time is reduced, but current source generator limits the pull-up current
Solution Approach 1:
The patent implements dynamic control of the current source generator, allowing it to adjust its current output based on the operational phase. During dark condition settling, the current source provides enhanced pull-up current to speed up settling, while during normal operation it maintains stable bias current. This dynamic adjustment resolves the conflict between settling speed and current limitation.
4Illumination intensity
If higher contrasts in light intensities occur, then larger voltages drops on bitline occur, but this directly leads to longer settling time
Solution Approach 1:
The patent uses parameter changes by dynamically adjusting the clamp voltage and bias current based on the detected light intensity contrast. When high contrast conditions are detected, the system increases the clamp voltage and adjusts the bias current to compensate for larger voltage drops, thereby maintaining fast settling times even under high contrast lighting conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces settling time and maintains stable power consumption, improving image quality by minimizing FPN and bitline RC delay, especially under high lighting conditions, while avoiding complex circuitry and power consumption issues.
Implementation Method 1
photo-generated electrons in each of the plurality of pixel cells are transferred from the photodiode (PD) to the floating diffusion (FD)
Implementation Method 2
Due to an always-presented coupling capacitance between the TX gate terminal and the FD, the pulse signal asserted on the TX gate is always largely coupled to the FD
Implementation Method 3
For any given bitline, since it connects to all the pixels in the column, it possesses a significant amount of capacitive and resistive (RC) load. Therefore, any state changes on the bitline are unavoidably slow due to this RC delay
Data Source
AI summary
A photodiode is adapted to accumulate image charges in response to incident light. The accumulate image charges are transferred to a floating diffusion, amplified, row selected and the amplified row selected signal is output to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. A current source is coupled to connect between the bitline source node and a ground. The current source generator sinks adjustable current from the bitline source node to the ground through a cascode transistor and a bias transistor. A cascode hold capacitor is coupled between the cascode control voltage and the ground. A bias hold capacitor is coupled between the bias control voltage and the ground. A bias boost driver is coupled to control the cascode control voltage and the bias control voltage.