Bitline Circuits for Embedded Charge Trap Memory
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Solution Overview
Problem
Conventional embedded non-volatile memory technologies, such as eFUSE, are inefficient in area scaling and require complex additional process elements, leading to high costs and limitations in high-performance logic technologies, while high-density memories like NAND or NOR flash introduce undesirable device structures and parasitics.
Innovation Solution
The development of bitline circuits for an embedded Multi-Time-Programmable-Read-Only-Memory (eMTPROM) using charge trap behavior in MOSFET devices, which controls charge trapping and detection in N-type MOSFET arrays without floating gates, employing mode-dependent pull-down circuits and sense amplifiers to optimize charge trap efficiency and signal development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional eFUSE is used for embedded non-volatile memory, then one-time programmability is achieved, but area efficiency deteriorates and device complexity increases
Solution Approach 1:
The invention changes the electrical parameters of standard CMOS transistors by trapping charges in the oxide layer, thereby modifying the threshold voltage to store data. This approach uses parameter changes rather than structural modifications, achieving non-volatile storage without requiring additional memory-specific device structures, thus improving area efficiency while maintaining programmability
2Quantity of substance
If floating gate or ultra-thick oxide structures are added for high density nonvolatile memory, then storage density is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The invention extracts the essential storage function from complex floating gate structures and implements it using simple charge trapping in the oxide layer of standard CMOS transistors. By removing the floating gate structure and using only the gate oxide as the storage medium, the invention achieves high-density storage with minimal device complexity, compatible with standard CMOS fabrication processes
Solution Approach 2:
The invention uses the naturally present gate oxide in CMOS transistors as a disposable storage medium that can be programmed by trapping charges. This approach treats the oxide layer as a consumable resource that can be modified during programming but requires no additional expensive structures, enabling high-density storage with standard logic technology processes
3Ease of operation
If high voltages greater than 5V are used for charge trapping, then programming capability is improved, but compatibility with high-performance logic technologies deteriorates
Solution Approach 1:
The invention uses dynamic voltage control through mode-dependent pull-down circuits that adjust the bitline voltage based on the operating mode (read, program, or erase). During programming, the circuit dynamically raises the bitline voltage to enable charge trapping, then returns to standard logic voltage levels, allowing high-voltage programming capability while maintaining compatibility with standard logic technology voltage levels during normal operation
4Productivity
If mode-dependent pull-down circuits are used for charge trapping, then charge trap efficiency is improved, but signal development during read mode deteriorates
Solution Approach 1:
The mode-dependent pull-down circuit dynamically adjusts its operation based on the current mode. During programming, it provides strong pull-down to efficiently trap charges. During reading, it transitions to a high-impedance state that allows the bitline voltage to float and develop properly in response to the charge trap state, enabling both efficient programming and accurate reading without compromising either function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient charge trapping and detection in eMTPROM, improving area efficiency and reducing costs by eliminating the need for complex additional process elements, while maintaining high performance in logic technologies.
Implementation Method 1
The bitline circuits control the bitline voltage to trap the charge (also referred to as electrons or e−) in a dielectric of the targeted NMOS
Implementation Method 2
The bitline is also employed for detecting the trapped state by developing a VT0 and VT1 dependent voltage on the bitline
Implementation Method 3
The BL voltage is strongly discharged to GND for an effective charge trapping during Programming mode
Implementation Method 4
The bitline circuits preferably use a bitline high voltage (VBLH) raised to an elevated bitline voltage (EBLH) when in said Programming mode, which results in an effective charge trapping in a Programming mode
Data Source
AI summary
A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.