Memory Device Current Measurement for Faster Program Verification
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Solution Overview
Problem
Existing memory devices face challenges in reducing the time required for program operations, particularly in multi-level cell methods where multiple program loops are necessary due to variations in programming speeds among memory cells.
Innovation Solution
A memory device with a current measurer and logic circuit that calculates the number of inhibit cells based on total current values, allowing for the omission of verify operations in certain program loops, thereby optimizing the verify process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verify operations are performed in all program loops to ensure data accuracy, then reliability is improved, but program operation time increases
Solution Approach 1:
The patent changes the parameter of verify operation execution from a fixed condition (always execute) to a dynamic condition based on the number of inhibit cells. When the number of inhibit cells is below a threshold, the verify operation is omitted, allowing the system to adapt the verification level based on actual memory cell states and reduce unnecessary time consumption.
Solution Approach 2:
The patent introduces dynamic control of the verify operation based on real-time detection of inhibit cell counts. The logic circuit dynamically adjusts whether to perform verify operations in subsequent program loops based on the initial inhibit cell detection, making the verification process flexible rather than static.
2Manufacturing precision
If multiple program loops are performed to program memory cells to various target levels, then manufacturing precision is improved, but program operation time increases
Solution Approach 1:
The patent performs a preliminary detection of inhibit cells before executing subsequent program loops. This preliminary action allows the system to identify memory cells that already meet the target level requirements and exclude them from further programming and verification, thereby reducing the total number of program loop iterations needed while maintaining precision.
Solution Approach 2:
Instead of performing complete verify operations on all memory cells in each program loop, the patent applies partial verification only to non-inhibit cells when necessary. This partial action approach maintains the required manufacturing precision for cells that need programming while avoiding redundant operations on cells that already meet specifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall time required for program operations by selectively omitting verify steps, enhancing efficiency and speed in memory device programming.
Implementation Method 1
a current measurer configured to output a total current value of the plurality of bit lines according to a sensing voltage measured from the plurality of bit lines
Data Source
AI summary
The present technology includes a memory device and a method of operating the same. The memory device includes a memory block, page buffers connected to memory cells through bit lines and configured to apply a program allowable voltage or a program inhibit voltage to the bit lines, a current measurer configured to output a total current value of the bit lines according to a sensing voltage measured from the bit lines, and a logic circuit configured to control the voltage generator and the page buffers to calculate the number of inhibit cells according to the total current value and omit a verify operation of a program loop or perform the verify operation of the program loop according to the number of the inhibit cells.