Bitline Current Split Circuit for Faster Nonvolatile Memory Reads
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Solution Overview
Problem
Flash and resistive memory devices experience increased precharge times due to coupling noises between bitlines during read operations, leading to inefficiencies in data retrieval.
Innovation Solution
A nonvolatile memory device with a current control switch circuit that generates a control current to increase the bitline current, reducing precharge and develop times by electrically connecting bitlines to a power supply and a sink node during specific periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a predetermined voltage or current is applied to bitlines for precharge operation, then the bitline is prepared for reading, but the precharge time is increased due to coupling noises between bitlines
Solution Approach 1:
The bitline current is segmented into two separate currents: a cell current that flows through the memory cell string to the source line, and a control current that flows through the current control switch circuit to the sink node. This segmentation allows independent optimization of each current path, enabling the control current to compensate for coupling noises without affecting the cell reading operation.
Solution Approach 2:
The current control switch circuit acts as an intermediary component that generates and controls the control current. This intermediary circuit is specifically designed to provide the additional current needed to overcome coupling noises between bitlines, thereby reducing precharge time while maintaining reliable read operations.
2Loss of time
If bitline current is increased to reduce precharge time, then coupling noises are compensated, but additional operations to determine cell state are required
Solution Approach 1:
The precharge operation and the coupling noise compensation are merged into a single unified operation. By generating the control current through the current control switch circuit during the precharge period, the patent simultaneously prepares the bitline for reading and compensates for coupling noises, eliminating the need for separate compensation operations.
Solution Approach 2:
The current control switch circuit automatically generates the control current based on the bitline current during the precharge period. The circuit self-regulates to provide the necessary current compensation without requiring external control operations or additional steps to determine cell state, thereby reducing operational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces precharge and develop times, enhancing the performance and reducing performance deviations of the nonvolatile memory device by increasing bitline current and optimizing sensing operations.
Implementation Method 1
a precharge transistor configured to electrically connect the bitline to a power supply voltage during a precharge period of a read operation to transmit a bitline current flowing from the power supply voltage to the bitline
Implementation Method 2
a cell string connected between the bitline and a source line, the cell string including a plurality of memory cells and being configured to transmit a first portion of the bitline current as a cell current
Implementation Method 3
a current control switch circuit connected between the bitline and a sink node, the current control switch circuit being configured to transmit a second portion of the bitline current as a control current flowing from the bitline to the sink node during the precharge period
Data Source
AI summary
A nonvolatile memory device is provided. The nonvolatile memory device includes: a bitline; a precharge transistor configured to electrically connect the bitline to a power supply voltage during a precharge period of a read operation to transmit a bitline current flowing from the power supply voltage to the bitline; a cell string connected between the bitline and a source line, the cell string including a plurality of memory cells and being configured to transmit a first portion of the bitline current as a cell current; and a current control switch circuit connected between the bitline and a sink node, the current control switch circuit being configured to transmit a second portion of the bitline current as a control current flowing from the bitline to the sink node during the precharge period.