Bitline Damage Detection Using Page Buffering Circuit
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Solution Overview
Problem
The existing methods for testing non-volatile memory devices are time-consuming due to the need for computation to configure defective memory cell addresses, especially when defects like short circuits or open circuits occur in bitlines during manufacturing, which can lead to defective memory cells.
Innovation Solution
A method that quickly identifies damaged bitline addresses by dividing bitlines into groups, applying voltages to test for open and short circuits, and using a page buffering circuit to store and read status data, thereby eliminating the need for complex address calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a computation process is used to configure the address of a defective memory cell, then the testing process can identify defective cells, but the process becomes time-consuming
Solution Approach 1:
The patent applies preliminary action by pre-configuring the page buffering circuit to automatically capture and store damaged bitline addresses during the testing process. Instead of performing computation after testing to identify defective cells, the system prepares the buffering circuit in advance to directly latch addresses when damage is detected, eliminating the need for time-consuming address calculation processes
Solution Approach 2:
The page buffering circuit performs self-service by automatically comparing test results with stored address information and autonomously latching the damaged bitline addresses. The circuit serves itself to identify defective cells without requiring external computation processes, thereby reducing testing time while maintaining identification accuracy
2Volume of moving object
If bit lines are placed closer together to reduce device dimensions, then the memory device size decreases, but short circuits between adjacent bit lines become more likely
Solution Approach 1:
The patent applies segmentation by dividing the bit line testing into systematic groups and using the page buffering circuit to individually track and identify damaged addresses. This segmentation approach allows precise identification of which specific bit lines are damaged, enabling targeted repairs or corrections while maintaining overall device reliability despite the increased risk from closely spaced bit lines
3Measurement precision
If a comprehensive testing process is performed to detect both open circuits and short circuits, then bit line damage detection accuracy improves, but the testing complexity increases
Solution Approach 1:
The patent applies universality by designing the page buffering circuit to perform multiple functions: it stores bitline addresses, compares test results, identifies both open circuits and short circuits, and automatically latches damaged addresses. This multi-functional circuit reduces testing complexity by consolidating what would otherwise require multiple separate testing and analysis processes into a single integrated system
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method streamlines the identification of damaged bitlines, reducing the time required for testing and enabling direct latching of damaged addresses, thus speeding up the examination process and avoiding the need for time-consuming programming or erasing processes.
Implementation Method 1
storing in a page buffering circuit a status data about damaged bit line addresses
Implementation Method 2
applying a supply voltage to the first-group bit lines via the first end thereof so as to perform a charge process and applying a ground voltage to the second-group bit lines
Data Source
AI summary
A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.