Bitline Discharge Control Circuitry for SRAM Read-Write Timing
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Solution Overview
Problem
Write failures occur due to false reads caused by timing mismatches between row and column select lines, especially at higher core voltages, leading to bitline discharge issues in memory operations, which impact cycle times and success of write operations in SRAM designs.
Innovation Solution
The implementation of bitline discharge control circuitry that sets a discharge boundary at a source voltage level minus a threshold voltage, preventing bitline discharge during read operations and ensuring faster recovery, thus preventing write failures and optimizing read/write cycle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precharging bitlines back to VDD before write operation, then write failure is reduced, but read/write cycle time is impacted
Solution Approach 1:
The patent introduces a discharge boundary voltage level (VBND) between GND and VDD, allowing bitlines to be discharged only up to this boundary rather than fully to GND. This parameter change enables faster recovery since the bitlines don't need to be precharged as much, reducing the read/write cycle time while still preventing false reads that cause write failures.
2Speed
If bitline discharge is allowed during read operation, then read operation is faster, but false read occurs causing write failure
Solution Approach 1:
The patent applies preliminary anti-action by establishing a discharge boundary voltage level (VBND) before read operations occur. The bitline discharge control circuitry prevents the bitline voltage from dropping below VBND during read operations, thereby preemptively avoiding the false read condition that would lead to write failure, while still allowing sufficient discharge for normal read operation.
3Power
If higher core voltage is used, then power performance is improved, but timing mismatch between row and column select lines causes false read
Solution Approach 1:
The patent introduces an intermediary discharge boundary voltage level (VBND) that mediates between the high core voltage (VDD) and ground (GND). This intermediate voltage level allows the system to operate at higher core voltages for better power performance while the discharge boundary control prevents timing mismatch issues from causing false reads, as the bitline voltage is constrained to stay above VBND regardless of timing variations.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.