Bitline Driver Isolation from Page Buffer Circuitry
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Solution Overview
Problem
In memory sub-systems, the time required for pre-charging bitlines during memory access operations introduces latency, delaying the initiation of pre-charging and voltage application to wordlines, which negatively impacts performance and quality of service.
Innovation Solution
Implementing bitline driver isolation from page buffer circuitry using an isolation element and a dynamic memory element, allowing pre-charging to occur concurrently with subsequent calculations, reducing latency by disconnecting the logic element from the dynamic memory element during pre-charging operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If bitline driver is connected to page buffer circuitry for calculations, then calculation results can be generated, but latency increases due to sequential operation
Solution Approach 1:
The patent applies preliminary action by performing calculations in advance during idle periods. The bitline driver performs calculations during the pre-charge interval before memory access operations, so that calculation results are ready before they are needed. This eliminates the sequential dependency where calculations must wait for pre-charging to complete, thereby reducing latency and improving memory access performance.
2Reliability
If pre-charging operations are performed before memory access, then bitlines are properly charged, but the process delays subsequent operations
Solution Approach 1:
The patent implements continuity of useful action by overlapping the pre-charging operation with subsequent calculation operations. While the bitline driver is pre-charging the bitlines, the page buffer circuitry continues to perform calculations using stored data. This parallel execution ensures that both pre-charging and calculations proceed simultaneously, eliminating idle time and maintaining continuous productive operation throughout the memory access cycle.
Data Source
AI summary
A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The circuit coupled to the dynamic memory element can perform a first operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.