Bitline Floating Circuit for SRAM Leakage Reduction
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Solution Overview
Problem
Current techniques for reducing leakage power in memory arrays, such as SRAM, are inadequate and increase design overhead, as they involve precharging bitlines to full Vcc, leading to excessive power consumption and design limitations, including accelerated oxide wear-out and limited design flexibility.
Innovation Solution
Implementing a bitline floating circuit that uses OR-gate logic and a wake signal to selectively float bitlines when not accessed, reducing leakage power by qualifying conventional precharge control signals, thereby enabling a PMOS-based power conserving sleep mode with minimal design overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bitlines are precharged to full Vcc when arrays are not accessed, then the bitlines are ready for immediate access, but leakage power consumption increases significantly
Solution Approach 1:
The patent applies dynamics by making the bitline voltage state changeable between two modes: precharged to Vcc for immediate access readiness, and discharged to floating state for power conservation. The bitline voltage is dynamically adjusted based on whether the array is actively accessed or in sleep mode, resolving the contradiction between speed and energy loss.
2Loss of energy
If NMOS and PMOS prechargers are used to limit bitline voltage, then leakage power is reduced, but design overhead increases significantly
Solution Approach 1:
The patent extracts the unnecessary complexity of dual NMOS and PMOS precharger circuits by removing them entirely. Instead, it uses a simpler discharge circuit with a control signal to achieve the same leakage reduction effect, thereby maintaining energy efficiency while significantly reducing design overhead.
3Power
If bitlines are precharged to full Vcc, then full voltage is available for operations, but oxide wear-out accelerates and design flexibility is limited
Solution Approach 1:
The patent applies periodic action by alternating the bitline voltage state between full Vcc (during active access) and discharged/floating state (during sleep mode). This periodic switching reduces the cumulative exposure time of the oxide to high voltage stress, thereby slowing down wear-out and improving reliability while maintaining full voltage availability when needed.
Data Source
AI summary
Techniques are disclosed that allow for power conservation in integrated circuit memories, such as SRAM. The techniques can be embodied in circuitry that allows for floating of bitlines to eliminate or otherwise reduce power leakage associated with precharging bitlines. For instance, the techniques can be embodied in a bitline floating circuit having a single logic gate for qualifying the precharge control signal with a wake signal, so that precharging of the bitline does not occur if the wake signal is not in an active state. The techniques further allow for the elimination or reduction of unnecessary power consumption by the I/O circuitry or the memory array, such as when the memory array is not being accessed or when the array or a portion thereof is permanently disabled for yield recovery.