Bitline Settling and FPN Reduction via Floating Pixel Disconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High dynamic range image sensors face issues with fixed pattern noise (FPN), slow bitline settling times, and unstable power supply due to capacitive and resistive loads, especially under varying lighting conditions, which affect image quality and sensor performance.
Innovation Solution
The implementation of a pixel output circuit with a clamp voltage generator and a blacksun voltage generator, along with an idle voltage generator, to control the bitline voltage and maintain stable power supply, allowing for fast settling of the bitline during image signal readout by disconnecting and reconnecting the pixel cell from the output line, and using adjustable currents to minimize voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the bitline is connected to all pixels in the column, then the pixel output can be read out, but the RC load causes slow settling time
Solution Approach 1:
The patent segments the bitline connection by introducing a switchable disconnect mechanism. The pixel cell can be disconnected from the bitline during charge transfer operations, separating the readout function from the charge transfer function. This allows the bitline to be isolated during critical settling periods while maintaining connectivity during readout operations.
2Object-affected harmful factors
If a clamp voltage generator is used to limit bitline voltage swing, then FPN is reduced, but large current variation occurs on power supply
Solution Approach 1:
The patent implements a dynamic clamp voltage generator that adjusts its operating state based on real-time bitline conditions. The clamp circuit transitions between active and inactive states, and adjusts clamping strength dynamically during different phases of pixel operation (photodetection, charge transfer, readout). This dynamic operation reduces power consumption while maintaining FPN suppression effectiveness.
3Loss of time
If the pixel cell is disconnected from the bitline during charge transfer, then settling time is reduced, but the bitline voltage control becomes more complex
Solution Approach 1:
The patent introduces an intermediary disconnect switch between the pixel cell and the bitline. This switch acts as a mediator that isolates the pixel cell from the bitline during charge transfer operations, preventing direct interaction that would cause voltage fluctuations. The switch is controlled by timing signals that coordinate with the pixel operation phases, simplifying the overall control logic while achieving fast settling.
4Adaptability or versatility
If multiple photodiodes are used for HDR, then dynamic range is improved, but fill factor is reduced
Solution Approach 1:
The patent merges multiple photodiode outputs into a shared readout path using the disconnect switch mechanism. During photodetection, all photodiodes accumulate charge independently. During charge transfer, the disconnect switch isolates the bitline, allowing multiple photodiodes to transfer charge simultaneously without interfering with each other. This merging approach enables HDR functionality while maintaining high fill factor for each individual photodiode.
Data Source
AI summary
A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.