Vertical Bitline Contact Junction Formation With Frontside Hot Implant
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Solution Overview
Problem
Current methods for forming graded junctions and low contact resistance for bitline of vertical contact transistors (VCTs) are ineffective due to lower temperature constraints during wafer backside processing, leading to inadequate dopant activation and diffusion.
Innovation Solution
A method involving delivering ions into the front side of a substrate at a temperature greater than 400°C to form a graded junction, followed by thermal treatment and epitaxial layer formation, which allows for effective dopant activation and diffusion without the need for additional annealing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ions are delivered into the substrate at lower temperatures during wafer backside processing, then the backside can be processed without damage, but dopant activation and diffusion are ineffective
Solution Approach 1:
The patent inverts the conventional processing sequence by performing ion implantation and thermal treatment on the frontside of the substrate before backside processing. This reversal allows the substrate to be heated to high temperatures (greater than 400°C) during frontside processing to achieve effective dopant activation, while avoiding the need to maintain low temperatures during backside processing. The graded junction is formed and thermally treated on the frontside, eliminating the temperature constraint that previously hindered dopant activation.
2Manufacturing precision
If the substrate is heated to high temperatures for effective dopant activation, then dopant diffusion improves, but the backside substrate may be damaged
Solution Approach 1:
The patent segments the processing into distinct frontside and backside operations. The high-temperature ion implantation and thermal treatment steps are performed on the frontside to achieve effective dopant activation and graded junction formation. After these frontside processes are complete, the substrate is then processed on the backside at lower temperatures. This segmentation allows high temperatures to be applied when needed for dopant activation without exposing the backside to damaging thermal conditions.
Solution Approach 2:
The patent performs the high-temperature ion implantation and thermal treatment as preliminary actions on the frontside before proceeding to backside processing. By completing the dopant activation and graded junction formation in advance on the frontside, the substrate is prepared for subsequent backside processing without requiring high temperatures during those later steps. This preliminary action eliminates the need to maintain low temperatures during backside processing while still achieving effective dopant activation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a high surface doping concentration graded junction, reducing contact resistance and improving the effectiveness of bitline contacts in VCTs for DRAM applications.
Implementation Method 1
delivering ions into a front side of a substrate of a transistor to form a graded junction in the substrate
Implementation Method 2
thermally treating the graded junction
Implementation Method 3
effective dopant activation and diffusion
Implementation Method 4
forming an epitaxial layer over the graded junction
Data Source
AI summary
Approaches herein provide devices, systems, and methods of transistor patterning using a frontside implant plus epitaxial process to form a graded junction having a high surface doping concentration for a vertical contact transistor bitline. One method may include delivering ions into a front side of a substrate of a transistor to form a graded junction in the substrate, wherein the substrate is maintained at a temperature greater than 100° C. while the ions are delivered into the substrate, and thermally treating the graded junction. The method may further include forming, after the graded junction is thermally treated, an epitaxial layer over the graded junction, forming a plurality of gates in the epitaxial layer, and processing a backside of the substrate to remove the substrate to the graded junction following formation of the plurality of gates.