Low-k Bitline Spacer Formation for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in providing effective isolation structures for nanoscale components, leading to increased parasitic capacitances and active power consumption.
Innovation Solution
The formation of spacers made of SiCO or porous materials with controlled carbon concentration and dielectric constant, utilizing etching selectivity and thermal treatment to create voids, simplifying the manufacturing process and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional isolation structures are used in nanoscale semiconductor devices, then device isolation is provided, but parasitic capacitances increase and active power consumption increases
Solution Approach 1:
The patent employs porous low-k dielectric materials for spacer formation, where the porous structure reduces the effective dielectric constant of the material. This lowers parasitic capacitance between conductive elements while maintaining adequate isolation, thereby reducing active power consumption in nanoscale semiconductor devices
Solution Approach 2:
The patent uses composite dielectric materials with tailored properties, combining different materials to achieve optimal dielectric constants and mechanical properties. The composite approach allows customization of electrical characteristics to minimize parasitic capacitance while maintaining structural integrity for device isolation
2Object-affected harmful factors
If spacers with low dielectric constant are formed, then parasitic capacitances are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent incorporates porogen addition during the conformal dielectric layer formation step, so that the porous structure is built-in during deposition rather than requiring separate porification steps. This preliminary incorporation of porogens simplifies the overall manufacturing process while achieving low-k spacers
Solution Approach 2:
The patent combines multiple functions into the spacer structure: electrical isolation, mechanical support, and stress management. By integrating these functions into a single low-k spacer component formed through combined processes (conformal deposition + porogen incorporation), the manufacturing complexity is reduced compared to implementing separate structures for each function
3Object-affected harmful factors
If carbon concentration in SiCO spacer is increased, then dielectric constant is reduced, but etching selectivity may be affected
Solution Approach 1:
The patent optimizes the carbon concentration parameter in SiCO spacers to achieve the desired dielectric constant while maintaining adequate etching selectivity. By carefully controlling the carbon content within specific ranges during deposition, the patent balances electrical performance (low parasitic capacitance) with manufacturability (etching selectivity)
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Low-k spacers are achieved, reducing active power consumption and improving performance by minimizing parasitic capacitances while lowering manufacturing costs.
Implementation Method 1
removing the remaining portion of the sacrificial layer comprises using an oxygen plasma to etch the remaining portion of the sacrificial layer
Implementation Method 2
heating the spacer to remove the porogens in the dielectric material to form voids in the dielectric material
Data Source
AI summary
A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a semiconductive feature therein; forming a first spacer adjacent to a sidewall of the bitline; forming a dielectric layer over the bitline; and after forming the dielectric layer, forming a contact adjacent to the first spacer and the dielectric layer and connected to the semiconductive feature of the semiconductor structure.