Bit-Line Pre-Charge Circuit Using Charge Sharing
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Solution Overview
Problem
Conventional bit-line pre-charge schemes in memory arrays are inefficient due to high bit-line capacitance, leading to prolonged pre-charge times and reduced operation speed, especially as the gate-to-source voltage of the charge transistor decreases during the pre-charge process, necessitating larger transistors that increase chip area.
Innovation Solution
A bit-line pre-charge circuit employing charge sharing between a capacitor and bit-line, where a capacitor is initially charged with a higher voltage and then shares charges with the bit-line, allowing for faster pre-charge through a smaller charge transistor, maintaining the bit-line voltage and reducing the size of the switch required for pre-charge, thus minimizing chip area and enhancing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional charge transistor pre-charge scheme is used, then the bit-line can be pre-charged to the target voltage, but the pre-charge time becomes excessively long when bit-line capacitance is high
Solution Approach 1:
The patent applies preliminary action by pre-charging a dedicated capacitor to a voltage higher than the target bit-line voltage before the actual pre-charge operation. This pre-prepared charged capacitor then rapidly transfers its charge to the bit-line through a switch, achieving fast pre-charge without relying on the slow conventional charge transistor. The capacitor is recharged from the bias voltage source after each use, maintaining the cycle of rapid pre-charge operations.
2Speed
If a large charge transistor is used to accelerate pre-charge, then the pre-charge speed improves, but the chip area increases
Solution Approach 1:
The patent introduces a capacitor as an intermediary energy storage element between the bias voltage source and the bit-line. Instead of using a large charge transistor to directly charge the high-capacitance bit-line, the capacitor is first charged to a higher voltage and then rapidly discharges into the bit-line through a small switch. This intermediary approach enables fast pre-charge with minimal transistor size, dramatically reducing chip area while maintaining high speed.
3Quantity of substance
If the bit-line is long with high capacitance, then more memory cells can be connected, but the pre-charge time increases significantly
Solution Approach 1:
The patent changes the voltage parameter by charging the capacitor to a voltage higher than the target bit-line voltage (e.g., 1.2V or 1.5V instead of 0.6V). This higher voltage differential creates a stronger driving force for charge transfer, enabling the capacitor to rapidly charge even long bit-lines with high capacitance. The voltage parameter change allows the system to maintain fast pre-charge times regardless of bit-line length or memory cell count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly accelerates the pre-charge process by maintaining high charging speed throughout, even when the bit-line is nearly fully charged, without increasing the chip area, thereby improving memory array operation speed.
Implementation Method 1
A bit-line pre-charge circuit and the method of pre-charging bit-lines of a memory array are provided
Data Source
AI summary
A device includes a first switch configured to control a connection between a first voltage node and a capacitor, and a second switch configured to control a connection between a common charge node and the capacitor. The device further includes a plurality of bit-lines, and a plurality of bit-line charge switches, each configured to control a connection between a respective one of the plurality of bit-lines and the common charge node.