Bitline Pull-Up Voltage Circuit for Low-Power Memory Access
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) face high power consumption when accessing memory cells due to the difference in supply voltage between memory cells and pull-up voltage circuits, leading to excessive current flow and increased energy usage during read or write operations.
Innovation Solution
A pull-up voltage circuit is designed with an inverter powered by a first supply voltage, utilizing p-type and n-type transistors to precharge bitlines in a memory device array, with a second supply voltage level that is lower than the memory cells' voltage, allowing for efficient voltage sensing and shut-off, reducing power consumption by transitioning to a diode-coupled mode of operation when the bitline voltage exceeds a reverse bias voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a pull-up voltage circuit uses a lower supply voltage than memory cells, then power consumption increases due to current flow from higher to lower voltage
Solution Approach 1:
The patent introduces a voltage leveler circuit as an intermediary component between the pull-up voltage circuit (operating at first supply voltage) and the memory cells (operating at second supply voltage). This voltage leveler raises the voltage from the first supply level to the second supply level, allowing the pull-up circuit to operate at the lower voltage while still providing the necessary high voltage to memory cells during read operations, thereby eliminating the direct current path that caused excessive power consumption.
2Speed
If a pull-up voltage circuit precharges bitlines to a high voltage level, then read operation speed improves, but power consumption increases due to excessive current flow
Solution Approach 1:
The patent implements dynamic voltage control where the pull-up voltage circuit adaptively adjusts its operating voltage based on the operational state. During read operations, the circuit dynamically raises the bitline voltage to the required high level for fast sensing, then quickly returns to the lower standby voltage level when not in use. This dynamic operation allows fast read speeds when needed while minimizing power consumption during idle periods.
Solution Approach 2:
The pull-up voltage circuit operates in periodic cycles, activating at high voltage only during brief read operation intervals and remaining in a low-power standby state otherwise. This periodic activation pattern enables the system to achieve fast read speeds during active periods while significantly reducing average power consumption through extended low-power intervals between operations.
Data Source
AI summary
A pull-up voltage circuit and method for reducing power consumption therewith are described. A pull-up voltage circuit has an inverter powered by a first supply voltage. A first p-type transistor and an n-type transistor are commonly gated to receive output from a first output node of the inverter to a first input node. A source region of the n-type transistor is coupled to a ground. A drain region of each of the first p-type transistor and the n-type transistor are commonly coupled at a second output node. A second p-type transistor has a gate coupled to the second output node. A drain region of the second p-type transistor, a source region of the first p-type transistor, and an input of the inverter are all coupled to a line. A source region of the second p-type transistor is coupled to the first supply voltage.