Bitline Segmentation for NAND Flash Seed Voltage Boosting
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Solution Overview
Problem
As NAND technology scales, the efficiency of self-boosting in NAND flash memory devices decreases due to increased parasitic capacitance, leading to program disturb issues where inhibited memory cells are inadvertently programmed.
Innovation Solution
A method involving a precharge, boost, equalize, and lock-in phase to bias adjacent bitlines, utilizing capacitive coupling to maintain a higher voltage in inhibited bitlines, thereby reducing program disturb by optimizing the boosting ratio through segment data handling and bitline-bitline capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-boosting is used to enhance channel level in inhibited cells, then program disturb is reduced, but boosting ratio decreases due to increased parasitic capacitance as technology scales
Solution Approach 1:
The bitline is divided into multiple segments with separate control capabilities. By segmenting the bitline, the patent can independently control and boost voltage in specific segments corresponding to inhibited cells, thereby maintaining effective boosting ratio despite increased parasitic capacitance from technology scaling.
Solution Approach 2:
The patent applies different voltage levels and boosting strategies to different segments of the bitline based on their specific requirements. Inhibited cell segments receive enhanced boosting while programmed cell segments receive different treatment, optimizing the local boosting efficiency in each region.
2Reliability
If elevated voltage is applied to deselected wordlines to increase channel voltage, then inhibited cell integrity is maintained, but parasitic capacitance increases reducing coupling efficiency
Solution Approach 1:
The patent introduces intermediate voltage levels and intermediate coupling structures between the wordlines and bitlines. By using intermediate nodes and controlled coupling mechanisms, the system maintains effective voltage transfer while reducing the direct impact of parasitic capacitance between high-voltage wordlines and sensitive bitlines.
3Reliability
If seed voltage is placed on inhibited bitlines to provide initial voltage, then channel/source/drain region voltage is enhanced, but voltage control complexity increases
Solution Approach 1:
The patent designs the segmented bitline control structure to serve multiple functions: it provides seed voltage to inhibited cells, maintains voltage during programming operations, and enables independent control of different cell regions. This multi-functional approach reduces the need for separate control mechanisms for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the voltage in inhibited bitlines, reducing program disturb and maintaining the integrity of unprogrammed cells by effectively managing capacitance and voltage levels across the memory array.
Implementation Method 1
utilizing capacitive coupling to maintain a higher voltage in inhibited bitlines
Data Source
AI summary
A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.