Bitline Settling Speed Enhancement via Short Method
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Solution Overview
Problem
Image sensor bitline settling time is limited by RC delay, especially in large signal settling conditions, which affects the speed of readout and requires redesign to address bitline floating node swing fluctuation and floating diffusion coupling.
Innovation Solution
Implementing a differential bitline design with a bitline short method that uses capacitor charge redistribution and an additional b1_boost switch to quickly settle output nodes to a midpoint, reducing RC delay and improving settling speed by shorting output nodes and storing mismatch information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional bitline design is used, then device complexity is low, but bitline settling time is long due to RC delay
Solution Approach 1:
The patent divides the bitline into two separate bitlines (first bitline and second bitline) to form a differential bitline design. This segmentation allows independent control and settling of each bitline, reducing the settling time for each individual bitline while maintaining overall system functionality.
Solution Approach 2:
The patent introduces a bitline short switch as an intermediary component that can connect the two bitlines together. This intermediary element enables rapid equalization of voltage levels between bitlines during settling phase, significantly reducing RC delay without requiring complete redesign of the readout circuitry.
2Productivity
If bitline settling time is reduced, then readout speed improves, but floating node swing fluctuation and floating diffusion coupling become problematic
Solution Approach 1:
The patent employs a bitline short switch that is controlled based on the settling status of the bitlines. When voltage levels between bitlines differ significantly, the switch activates to equalize them, providing feedback control that ensures stable settling while maintaining fast readout speed.
Solution Approach 2:
The patent makes the bitline configuration dynamic by introducing a controllable short switch that can be activated or deactivated based on operational requirements. This dynamic adjustment allows the system to optimize between fast readout and signal stability depending on the settling phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces bitline settling time and enhances the performance of analog to digital converters during black and image signal average periods, improving the overall speed of image sensor readout.
Implementation Method 1
uses capacitor charge redistribution and an additional b1_boost switch to quickly settle output nodes to a midpoint
Implementation Method 2
Bitline settling time is limited by RC delay
Data Source
AI summary
An image sensor includes pixel circuitry with a photodiode to receive light and output a pixel signal. The image sensor also includes readout circuitry with a first sample and hold transistor coupled to the pixel circuitry, and a first capacitor coupled to the first sample and hold transistor to receive the pixel signal. A second sample and hold transistor is coupled to the pixel circuitry, and a second capacitor is coupled to the second sample and hold transistor to receive the pixel signal. A first output switch is coupled to output the pixel signal from the first capacitor, and a second output switch is coupled to output the pixel signal from the second capacitor. A boost transistor is coupled to connect the first output switch and the second output switch when the boost transistor is turned on.