Bitline Shunting Networks for Lower IR Drop in Memory Arrays
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Solution Overview
Problem
Limited memory bandwidth and high power consumption in machine learning systems, particularly in deep neural networks, due to the bottleneck at the interface between processor chips and DRAMs, leading to latency and inefficient data movement.
Innovation Solution
Integration of memory and processing in a single integrated circuit device using multi-pillar memory cells to reduce IR drops in bitlines, enabling efficient matrix vector multiplication and accumulation operations directly in the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-pillar memory cells are used to increase storage capacity, then memory bandwidth is improved, but IR drops in bitlines increase
Solution Approach 1:
The bitline is divided into multiple segments, and shunt circuits are inserted between adjacent segments to provide alternative current paths. This segmentation reduces the effective resistance along the bitline by creating parallel conduction paths, thereby reducing IR drops while maintaining high storage capacity through multi-pillar memory cells.
Solution Approach 2:
Shunt circuits are introduced as intermediary elements between bitline segments. These shunt circuits act as mediators that provide additional current conduction paths, reducing the overall resistance and IR drops in the bitline without compromising the storage functionality of the multi-pillar memory cells.
2Object-affected harmful factors
If shunt circuits are added to reduce IR drops, then bitline resistance is reduced, but device complexity increases
Solution Approach 1:
The shunt circuit is merged with the bitline structure, where the shunt path is integrated alongside the main bitline segments. This merging approach reduces IR drops by creating parallel conduction paths while minimizing the increase in device complexity through unified structural design.
Solution Approach 2:
Shunt circuits are strategically placed at specific locations along the bitline where IR drops are most significant. This localized approach addresses resistance issues at critical points without requiring uniform modification of the entire bitline structure, thereby reducing overall device complexity.
Data Source
AI summary
Systems, methods, and apparatus for memory devices having shunting networks connected to access lines. In one approach, a memory device has memory cells arranged in a memory array. The memory cells are accessed using bitlines that are formed overlying the array. The bitlines are coupled to a shunting network that reduces the effective resistance of the bitlines. This improves performance when performing matrix vector multiplication using the memory array.