Bitline Voltage Compensation in Non-Volatile Memory Program-Verify
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Solution Overview
Problem
Non-volatile memory systems face errors during data reading due to differences in IR drop between program-verify and reading processes, which are caused by varying bit line voltages, leading to inaccurate data retrieval.
Innovation Solution
Adjusting the bit line voltage during program-verify to compensate for different IR drops between program-verify and reading processes, ensuring accurate data reading by maintaining consistent voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bit line voltage is used for both program-verify and reading, then device complexity is reduced, but reading accuracy deteriorates due to IR drop differences between operations
Solution Approach 1:
The patent segments the bit line voltage control into operation-specific voltage levels: a first bit line voltage for program-verify operations and a second bit line voltage for reading operations. This segmentation allows each operation to have optimized voltage conditions, resolving the contradiction between using a single voltage (simple control) and using operation-specific voltages (accurate reading).
Solution Approach 2:
The patent changes the bit line voltage parameter based on the operation being performed. By adjusting the voltage level according to whether the operation is program-verify or reading, the system optimizes performance for each specific operation while maintaining overall system functionality.
2Measurement precision
If bit line voltage is adjusted for each memory block location, then reading accuracy is improved, but device complexity increases due to location-dependent voltage control
Solution Approach 1:
The patent applies local quality by assigning different bit line voltages to memory blocks based on their physical location relative to the bit line driver. Blocks farther from the driver receive different voltage levels than those closer to the driver, compensating for location-dependent IR drop variations and improving reading accuracy across the entire memory array.
Solution Approach 2:
The patent performs preliminary characterization of IR drop for each memory block location during manufacturing or initialization. This pre-measured data is stored and used to determine the appropriate bit line voltage for each block, allowing the system to compensate for location-dependent effects without real-time complex calculations.
3Measurement precision
If location-dependent bit line voltages are used during program-verify, then reading accuracy is improved, but ease of operation deteriorates due to complex voltage adjustment procedures
Solution Approach 1:
The patent implements self-service by having the control circuit automatically select and apply the appropriate bit line voltage for each memory block based on pre-stored IR drop characterization data. The system autonomously determines which voltage level to use for program-verify operations without requiring manual intervention or complex user decisions, maintaining ease of operation while achieving high reading accuracy.
Solution Approach 2:
The patent uses feedback from pre-characterized IR drop measurements to automatically adjust bit line voltages during program-verify operations. The control circuit references stored characterization data to determine the correct voltage level for each block, creating a closed-loop system that maintains accuracy without increasing operational complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data reading accuracy by minimizing errors resulting from voltage discrepancies, thereby improving the reliability of non-volatile memory systems.
Implementation Method 1
differences in IR drop between program-verify and reading processes
Data Source
AI summary
A non-volatile storage apparatus programs memory cells, including performing program-verify. The performing program-verify comprises applying location dependent bit line voltages to the bit lines connected to the memory cells. The location dependent bit line voltages are different in voltage magnitude for different locations based on distance from bit line drivers connected to the bit lines. The memory cells are read by applying, regardless of location, a common bit line voltage to the bit lines that is higher in voltage magnitude than the any of the location dependent bit line voltages. In one example implementation, the read process is used to perform in-memory vector-matrix multiplication.