Bitline Multi-Level Voltage Sensing with Op-Amp Feedback ADC
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Solution Overview
Problem
Multi-level DRAMs face challenges in accurately detecting changes in bit line voltages due to reduced voltage differences between reference and neighboring voltages, as well as the impact of temperature and noise.
Innovation Solution
A circuit for sensing multi-level voltages of a bit line is designed for multi-bit operations in DRAM, comprising a bit line connected to a memory cell, an operational amplifier, a feedback capacitor, and an analogue-to-digital converter, which enables precise detection of cell voltages despite temperature and noise variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a sense amplifier is used to read data in multi-level DRAM, then data can be read from the memory cell, but the voltage difference between reference voltage and neighboring reference voltages becomes smaller making it difficult to accurately detect bit line voltage changes
Solution Approach 1:
The patent segments the voltage detection process into multiple stages: pre-charging stage, sensing stage, and amplification stage. The sense amplifier is divided into multiple sub-amplifiers that independently process different voltage levels, allowing each segment to optimize for its specific function and improve overall detection precision.
Solution Approach 2:
The patent introduces intermediate voltage reference lines and buffer circuits between the bit line and the sense amplifier. These intermediary elements condition the voltage signals before they reach the amplification stage, enhancing the detectability of small voltage differences caused by multi-level charge sharing.
2Quantity of substance
If multi-level DRAM is used to store more than one bit per cell, then storage capacity increases, but the system cannot detect slight voltage changes precisely due to temperature or noise
Solution Approach 1:
The patent performs preliminary pre-charging of the bit line to a predetermined voltage level before the actual read operation. This preliminary action establishes a known baseline state, allowing the sense amplifier to detect only the voltage changes caused by charge sharing from the memory cell, thereby improving reliability against temperature and noise variations.
Solution Approach 2:
The patent implements feedback mechanisms where the output of the sense amplifier is fed back to adjust the reference voltages dynamically. This feedback loop compensates for drift caused by temperature changes and noise, maintaining reliable detection of slight voltage changes throughout operation.
3Ease of operation
If a differential inverter is formed between neighboring bit lines to detect voltage difference, then data reading is enabled, but detection precision deteriorates in multi-level DRAM with smaller voltage differences
Solution Approach 1:
The patent employs dynamic control of the differential inverter operating point by adjusting bias voltages during the read operation. The inverter is designed to operate in its most sensitive region where small voltage differences produce maximum output swing, thereby maintaining ease of operation while improving detection precision for multi-level voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively detects multi-level voltages of the bit line in multi-level DRAMs with high precision, regardless of temperature or noise, and allows direct detection of cell voltages, improving data reading accuracy.
Implementation Method 1
a feedback capacitor connected between an output end of the operational amplifier and the inverting input end thereof
Implementation Method 2
an operational amplifier including a noninverting input end connected to a pre-charging voltage line and an inverting input end connected to an opposite end of the 1-st switch
Implementation Method 3
an analogue-to-digital converter configured to convert an output voltage of the operational amplifier to a digital signal
Data Source
AI summary
The present invention relates to a bitline multi-level voltage sensing circuit for a multi-bit operation of a DRAM including a memory cell that stores data by an operation of a wordline and a bitline, the bitline multi-level voltage sensing circuit comprising: an operational amplifier having a non-inverting input terminal coupled to a precharging voltage line and an inverting input terminal coupled to a bitline through a first switch enabled by a wordline signal; a feedback capacitor formed between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier; a second switch formed in parallel with the feedback capacitor between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier and enabled by a precharging signal; and an analog-to-digital converter that converts an output voltage of the output terminal of the operational amplifier into a digital signal.