Bitstream Generation Deterrence for Integrated Circuits

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Solution Overview

Problem

Existing technologies are ineffective in deterring reverse engineering of configuration bitstreams for integrated circuit devices, which can lead to piracy and unauthorized use.

Innovation Solution

Implementing a method that checks for degenerate designs and active force settings, triggering reverse engineering countermeasures such as slowing or suspending bitstream generation if a trip point is exceeded, and updating deterrence information to prevent illicit use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If bitstream generation is allowed without restrictions, then legitimate uses can proceed efficiently, but reverse engineering and piracy occur

Engineering Contradiction:
Improvebitstream generation speedVSAvoidreverse engineering
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary actions by checking design characteristics and trip points before allowing bitstream generation. It monitors usage patterns in advance and triggers countermeasures before actual reverse engineering can occur, preventing harmful actions while maintaining legitimate operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms by continuously monitoring bitstream generation patterns, usage frequency, and design characteristics. When abnormal patterns are detected (exceeding trip points), the system adjusts behavior accordingly, slowing or suspending generation to deter reverse engineering while allowing legitimate uses to continue.

Inventive Principle:
Principle #23Feedback

2Object-affected harmful factors

If reverse engineering countermeasures are implemented, then piracy is deterred, but legitimate uses may be affected

Engineering Contradiction:
Improvereverse engineering deterrenceVSAvoidlegitimate use continuity
Core Design Contradiction:
Object-affected harmful factorsVSEase of operation

Solution Approach 1:

The system dynamically adjusts its behavior based on detected patterns. Rather than applying static restrictions, it monitors usage in real-time and only slows or suspends bitstream generation when reverse engineering patterns are detected. This dynamic approach maintains ease of operation for legitimate users while providing effective deterrence against piracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system applies different levels of protection to different usage scenarios. It allows normal, legitimate operations to proceed uninterrupted while applying additional monitoring and restrictions only when abnormal patterns are detected. This localized quality of protection minimizes impact on legitimate uses while maximizing deterrence effectiveness.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If monitoring and countermeasures are added to the bitstream generation process, then reverse engineering is deterred, but device complexity increases

Engineering Contradiction:
Improvereverse engineering preventionVSAvoidbitstream generation system
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The monitoring and countermeasure system serves multiple functions: it detects reverse engineering patterns, monitors usage patterns, tracks design characteristics, and provides feedback for adaptive protection. By making the system multi-functional, the patent reduces the need for separate dedicated components, thereby limiting the increase in overall device complexity while maintaining effective reverse engineering prevention.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8024688B1Deterring reverse engineering
Publication Date: 2011.09.20 XILINX INC
  • US8024688B1 patent drawing
  • US8024688B1 patent drawing
  • US8024688B1 patent drawing

AI summary

A method for detecting reverse engineering of a configuration bitstream for an integrated circuit is described. A user design is obtained. It is determined if the user design is a degenerate design. If the user design is a degenerate design, it is determined if a trip point for bitstream generation has been tripped. If the trip point for the bitstream generation has not been tripped, deterrence information is updated and the bitstream generation is allowed to take place. If the trip point for the bitstream generation has been tripped, at least one reverse engineering countermeasure is initiated.