Bitstream Fence Verification for PLD Electrical Isolation
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Solution Overview
Problem
Existing methods for verifying electrical isolation between regions in programmable logic devices (PLDs) are inadequate, particularly in cryptographic applications where errors during translation of circuit designs into bitstreams can compromise isolation, leading to potential security breaches.
Innovation Solution
A computer-implemented method that translates a circuit design into a bitstream, identifies unused routing resources, generates a fence bitstream specifying these resources, and compares it with the original bitstream to determine if regions are isolated, using logical operations to ensure accurate isolation and detect translation errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circuit design is translated into bitstream for PLD configuration, then the circuit can be implemented in the PLD, but translation errors can compromise electrical isolation between regions
Solution Approach 1:
The invention performs preliminary verification of electrical isolation by comparing the generated bitstream against a fence bitstream before the PLD is configured. This preliminary action detects translation errors that would compromise isolation, allowing correction before deployment and ensuring reliability of region isolation.
Solution Approach 2:
The fence bitstream serves as an intermediary verification mechanism. It represents the ideal isolation state and mediates the verification process by comparing against the actual bitstream, identifying any deviations that indicate translation errors compromising isolation.
2Measurement precision
If fence bitstream is generated and compared with circuit design bitstream, then translation errors can be detected, but additional verification steps increase processing time
Solution Approach 1:
The invention creates a fence bitstream as a copy representing the ideal isolation state. This copying approach enables efficient comparison using bitwise operations, providing precise detection of translation errors while maintaining relatively fast verification processing through optimized computational methods.
3Reliability
If all routing resources are specified in fence bitstream, then complete isolation verification is achieved, but bitstream size and complexity increase
Solution Approach 1:
The invention extracts only the essential fence routing resources that define region boundaries into the fence bitstream, rather than including all possible routing resources. This extraction maintains complete verification of electrical isolation while reducing bitstream size and complexity by focusing only on the critical isolation-defining routes.
Data Source
AI summary
A computer-implemented method of verifying electrical isolation of portions of a circuit design for a programmable integrated circuit (IC) can include translating a circuit design into a circuit design bitstream specifying a plurality of regions, wherein the regions are to be isolated from one another. Routing resources of the programmable IC that are not used by the circuit design can be identified. A fence bitstream can be generated that specifies the unused routing resources. The circuit design bitstream can be compared with the fence bitstream. An indication of whether the plurality of regions of the programmable IC are isolated can be output according to the comparison.