Bitstream Parsing Apparatus EPB Removal Double Buffer

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Solution Overview

Problem

Existing systems for decoding bitstreams, particularly in H.264/AVC, face performance reduction due to the need to remove Emulation Prevention Bytes (EPBs) from bitstreams, which requires sequential reading and reloading of bitstreams, leading to inefficient memory loading.

Innovation Solution

A bitstream parsing apparatus with an EPB processor, register buffer units, and an output buffer selection unit that detects and removes EPB patterns, allowing for sequential parsing and decoding while minimizing memory loading by using a double buffer structure to store and select between bitstreams with and without EPB patterns based on a buffer selection flag.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an EPB code is searched for and removed while sequentially parsing bitstreams, then the bitstreams can be decoded correctly, but the system performance is reduced due to memory loading overhead

Engineering Contradiction:
Improvedecoding correctnessVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by removing EPB codes from bitstreams before the main decoding process. The EPB removal unit detects and removes EPB codes (0x03) from the bitstream in advance, storing the cleaned bitstream in a buffer. This preliminary cleaning eliminates the need for repeated memory loading and re-parsing during decoding, thereby maintaining decoding correctness while significantly improving system performance.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If bitstreams are loaded in memory while overlapping for EPB removal, then EPB codes can be removed, but memory efficiency is reduced and performance decreases

Engineering Contradiction:
ImproveEPB removal capabilityVSAvoidmemory usage
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent applies the extraction principle by removing only the necessary EPB codes (0x03 bytes) from the bitstream without requiring overlapping memory loading. The EPB removal unit extracts and eliminates EPB codes in a single pass, storing the cleaned bitstream in a buffer. This approach eliminates the need for redundant memory operations while maintaining EPB removal capability, thereby reducing memory usage and improving efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Stability of the object's composition

If the same pattern as start code occurs in intermediate portion of NAL, then data integrity is maintained, but EPB removal is required which complicates the decoding process

Engineering Contradiction:
Improvedata integrityVSAvoiddecoding process complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing EPB removal before the main decoding process. The EPB removal unit detects and removes EPB codes (0x03) from the bitstream in advance, ensuring data integrity is maintained while the bitstream is cleaned. This preliminary processing simplifies the subsequent decoding process by eliminating the need for complex runtime EPB detection and removal logic, thereby reducing decoding process complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9014259B2Apparatus and method for sequentially parsing bitstreams based on removal of emulation prevention byte
Publication Date: 2015.04.21 SAMSUNG ELECTRONICS CO LTD
  • US9014259B2 patent drawing
  • US9014259B2 patent drawing
  • US9014259B2 patent drawing

AI summary

An apparatus and method sequentially parses bitstreams based on a removal of an Emulation Prevention Byte (EPB). The apparatus and method may detect an EPB pattern from among sequentially input bitstreams, may store the bitstreams, may store a processed bitstream where the EPB pattern is removed, among the bitstreams, and may select an output of a register buffer based on an input of a buffer selection flag.