Bitstream Syndrome Checking With Relocated Parity Bits
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Solution Overview
Problem
Existing error detection and correction methods for bitstream frames transmitted one word at a time in programmable logic devices, such as FPGAs, are inadequate for reliable error checking and correction, particularly in configurations exceeding a thousand bits, where single error correction and double error detection are insufficient.
Innovation Solution
A method and apparatus for decoding encoded information that computes partial syndrome values for each word of a bitstream frame, combining them with previously stored values to determine error locations and correct errors, utilizing a decoder with syndrome logic, feedback filters, and controllers to manage clock signals and error detection in programmable logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error checking methods are used for bitstream frames transmitted one word at a time, then the transmission can be simplified, but error detection and correction reliability is insufficient for configurations exceeding a thousand bits
Solution Approach 1:
The patent segments the bitstream frame into multiple words and processes them sequentially through the decoder. The syndrome computation is divided into partial syndromes for each word, which are then combined to form the final syndrome. This segmentation allows the decoder to handle large bitstream frames exceeding a thousand bits while maintaining reliability through systematic error detection and correction across all segments.
2Reliability
If parity bits are transmitted with data bits in conventional manner, then transmission structure is simple, but error checking capability is insufficient for sequential word transmission
Solution Approach 1:
The patent implements feedback mechanisms where the controller tracks the current word being processed and uses this information to control the syndrome computation process. The feedback filter and controller work together to ensure that partial syndromes are properly accumulated and combined based on the sequential word transmission, enabling reliable error checking without complicating the transmission operation.
3Reliability
If all bits of a bitstream frame are transmitted simultaneously, then error checking can be performed on the complete frame, but transmission time and hardware resources increase significantly
Solution Approach 1:
The patent enables continuous syndrome computation as each word is received, rather than waiting for the complete frame. The partial syndromes are accumulated in real-time, allowing the error checking process to continue throughout the transmission. This continuous action maintains error checking accuracy while significantly reducing transmission time and hardware resource requirements compared to simultaneous transmission of all bits.
Data Source
AI summary
Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.