Bitwise Arbitration Bridge for Serial Bus Collision Resolution

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Solution Overview

Problem

Existing data communication systems using a single serial bus face challenges with message collisions and synchronization, particularly in low data-rate systems, which limit their scalability and compatibility with higher data rates while maintaining backwards compatibility.

Innovation Solution

The method involves using non-destructive bitwise arbitration with dominant and recessive states on a serial bus, where nodes detect and transmit states at predetermined times, and a bridging device synchronizes data transfer between two buses, utilizing AC power synchronization to adjust bit rates for compatibility with both AC-synchronized and node-synchronized systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single serial signal path is used to reduce the number of conductors, then wiring complexity is reduced, but message collisions occur between simultaneous transmissions

Engineering Contradiction:

Improvewiring complexityVSAvoidmessage collision

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary arbitration mechanism that mediates between multiple nodes attempting to transmit on the serial bus. The arbitration system acts as a mediator that resolves conflicts by determining which node gains transmission rights, preventing message collisions while maintaining the single-bus architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements feedback through acknowledgment signals and arbitration responses. When a node transmits a message, it receives feedback about whether the transmission was successful or if a collision occurred, allowing the system to retry or adjust transmission timing to avoid future collisions.

Inventive Principle:

Principle #23Feedback

2Device complexity

If AC power synchronization is used to simplify node synchronization, then synchronization complexity is reduced, but data rate is limited to low speeds (120 or 100 bits per second)

Engineering Contradiction:

Improvesynchronization complexityVSAvoiddata rate

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent makes the synchronization system dynamic by allowing it to adapt between different modes. The system can operate in AC-synchronized mode for compatibility with legacy devices or switch to node-synchronized mode to achieve higher data rates, making the synchronization approach flexible rather than fixed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the synchronization parameter from fixed AC power line frequency to variable node-generated synchronization signals. This allows the system to adjust the synchronization rate and achieve higher data rates while maintaining the simplified synchronization approach.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If higher data rates are implemented to improve communication speed, then productivity is improved, but compatibility with legacy AC-synchronized devices is lost

Engineering Contradiction:

Improvecommunication speedVSAvoidbackwards compatibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal bus system that can function with both AC-synchronized legacy devices and node-synchronized high-speed devices. The arbitration mechanism and synchronization system are designed to accommodate multiple device types and operating modes, making the system multi-functional and backward compatible.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the bus system into different operational domains or zones, allowing AC-synchronized devices to operate in one mode while node-synchronized devices operate in another. The arbitration system manages these segmented operations, enabling high-speed communication among compatible devices while maintaining compatibility with legacy devices.

Inventive Principle:

Principle #1Segmentation

4Measurement precision

If elaborate synchronization mechanisms are used to maintain synchronized timing, then timing precision is improved, but device complexity increases

Engineering Contradiction:

Improvetiming precisionVSAvoidsynchronization mechanism complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements self-service synchronization where nodes automatically adjust their internal timers based on received bits without requiring complex external synchronization infrastructure. Each node independently maintains synchronization through simple timer adjustments triggered by received data, eliminating the need for elaborate centralized synchronization mechanisms.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS7680144B2Device coupled between serial busses using bitwise arbitration

Publication Date: 2010.03.16 RESIDEO USA LLC

AI summary

First and second serial data busses are arranged so that simultaneous transmission on the respective bus of a dominant state by one node and a recessive state by other nodes results in the dominant state being detectable on the respective bus. Transitions from a first state to a second state signal the start of a bit on the first bus. Dominant and recessive states are detected on the first and second busses at first and second predetermined times after each transition. The states represent respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses. The dominant state is transmitted on both busses after the first and second predetermined times if the dominant state was detected on one of the first and the second busses at the first and second predetermined times.