Bitwise Digital Filtering for Low-Power Frequency Analysis
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Solution Overview
Problem
Conventional digital circuitry for mobile and wearable devices consumes excessive power during frequency analysis and filtering operations, making it unsuitable for use in these devices due to power limitations and size constraints.
Innovation Solution
The implementation of bitwise operations to perform low-power digital filtering by approximating a Fourier transform through multiplication of input signals with encoded sinusoids, using a circular register and logical gate blocks to generate an output signal indicating the product of the input signal and the sinusoid, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional circuitry is used to perform frequency analysis and filtering operations, then the processing capability is sufficient, but the power consumption is excessive for mobile and wearable devices
Solution Approach 1:
The patent replaces conventional arithmetic-based digital signal processing circuitry with a neural network-based system. The neural network performs frequency analysis and filtering operations through pattern recognition and mathematical transformations inherent to neural network computations, substituting traditional mechanical/electrical signal processing mechanisms with a computational intelligence approach that achieves comparable or superior processing capability while reducing power consumption through optimized inference operations
Solution Approach 2:
The patent changes the operational parameters of the processing system by using fixed-point arithmetic with specific bit widths (e.g., 8-bit or 16-bit quantization) for neural network computations. This parameter optimization allows the system to achieve sufficient processing accuracy for frequency analysis while significantly reducing the computational complexity and power consumption compared to conventional floating-point or high-precision arithmetic operations
2Measurement precision
If conventional circuitry for frequency analysis is implemented, then accurate filtering can be achieved, but the device size increases which is unsuitable for mobile and wearable applications
Solution Approach 1:
The patent replaces conventional analog or digital filter circuitry with a neural network-based processing system. The neural network achieves accurate frequency analysis and filtering through learned patterns and transformations, substituting traditional filter hardware with a computational model that can be implemented more compactly, especially when using optimized neural network architectures and fixed-point arithmetic
3Volume of moving object
If mobile and wearable devices use smaller physical size, then portability is improved, but power consumption limits are reached more quickly
Solution Approach 1:
The patent optimizes power consumption by changing computational parameters to fixed-point arithmetic with carefully selected bit widths for neural network operations. This parameter optimization reduces the power requirements of the processing system, enabling compact mobile and wearable devices to perform frequency analysis and filtering operations within their power budgets while maintaining small physical size
Solution Approach 2:
The patent substitutes power-intensive conventional signal processing circuitry with a neural network-based system that can achieve comparable or superior processing efficiency. The neural network architecture, when implemented with optimized inference operations and fixed-point arithmetic, consumes less power than traditional DSP or FPGA-based frequency analysis systems, enabling smaller device size without exceeding power limits
Data Source
AI summary
Systems and devices are provided to perform low-power digital filtering of sensor or other data based on bitwise operations. A reference sinusoid is encoded via a plurality of pulse trains, such that each pulse train includes a number of pulses n representing a value of the reference sinusoid out of a maximum possible pulses corresponding to an encoding quantization level. A circular register stores a representation of the encoded sinusoid. A set of multiple logical gate blocks are configured to multiply, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the encoded sinusoid. A logic circuit coupled to the circular register and the set of multiple logical gate blocks is configured to generate, based on the encoded sinusoid and on the input signal, an output signal indicating an approximate value of the received input signal multiplied by the encoded sinusoid.