Bitwise MAC Accumulation with Skip Logic for ReLU Workloads

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Solution Overview

Problem

Existing implementations of multiply accumulate (MAC) operations in artificial neural networks, particularly for ReLU activation functions, are inefficient when executed on general-purpose processors and require inefficient use of binary math in digital logic blocks when implemented in hardware.

Innovation Solution

A skip module is introduced to simplify the computational complexity of MAC operations by evaluating a partial sum accumulation and predicting whether further computations are necessary based on a skip condition, using a bitwise processing approach.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If MAC operations are executed on general-purpose processors, then implementation flexibility is maintained, but computational efficiency and resource utilization deteriorate

Engineering Contradiction:
Improveimplementation flexibilityVSAvoidcomputational efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The MAC operation is segmented into multiple partial sum accumulations, each processing a portion of the weight bits. The skip module evaluates each partial sum independently to determine whether to skip remaining computations, enabling fine-grained optimization while maintaining overall computational correctness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The skip module performs preliminary evaluation of partial sum accumulations before completing full MAC operations. By assessing intermediate results and predicting whether further computations are necessary, the system avoids unnecessary computational cycles while ensuring accurate outcomes when needed.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If traditional binary math is used in digital logic blocks, then implementation simplicity is maintained, but resource wastage and computational overhead increase

Engineering Contradiction:
Improveimplementation simplicityVSAvoidresource wastage
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The system performs partial MAC operations by processing only necessary portions of weight bits. The skip module determines the exact point at which computations can be terminated, avoiding excessive processing while maintaining result accuracy. This partial action approach reduces resource wastage without requiring complete simplification of the computational logic.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The skip module enables the system to skip unnecessary computational steps by evaluating partial sum accumulations and predicting when further computations will not affect the final result. This rushing through of redundant operations significantly reduces computational cycles and resource consumption while maintaining implementation feasibility.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If all MAC operations are completed regardless of intermediate results, then computational accuracy is ensured, but computational cycles and time consumption increase

Engineering Contradiction:
Improvecomputational accuracyVSAvoidcomputational cycles
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The skip module implements feedback by continuously monitoring partial sum accumulations during MAC operations. Based on the evaluated intermediate results and predicted outcomes, the system dynamically determines whether to continue or skip remaining computations, ensuring accuracy is maintained only when necessary while reducing unnecessary computational cycles.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary evaluation of partial sum accumulations to predict whether complete MAC operations will affect the final result. This preliminary assessment allows the system to skip redundant computations confidently, reducing time consumption while maintaining computational accuracy through predictive analysis.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250348554A1Bitwise product-sum accumulations with SKIP logic
Publication Date: 2025.11.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250348554A1 patent drawing
  • US20250348554A1 patent drawing
  • US20250348554A1 patent drawing

AI summary

A method, device, and system for performing a partial sum accumulation of a product of input vectors and weight vectors in a wordwise-input and bitwise-weight manner results in a partial accumulated product sum. The partial accumulated product sum is compared with a threshold condition after each weight bit, and when the partial accumulated product sum meets the threshold condition, a skip indicator is asserted to indicate that remaining computations of a sum accumulation are skipped.