Bitwise Majority Vote Instruction for Radiation-Tolerant Processors

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Solution Overview

Problem

Electronic systems operating in harsh radiation environments face single-event upsets due to high-energy particles, which can corrupt digital information, necessitating improved fault tolerance and reliability in processor operations.

Innovation Solution

A system with triple modular redundancy using integrated circuits with three processors that perform bitwise majority vote and sum of two closest operations to correct single-event upsets, ensuring identical digital values across replicated signal paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If triple modular redundancy is employed with majority voting systems, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvefault toleranceVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the majority voting function directly into the processor instruction set architecture through a dedicated RMAJ instruction, merging the voting logic with the computational core rather than using separate external voting circuits. This integration reduces overall system complexity while maintaining triple modular redundancy for reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The processor performs its own majority voting operation through the RMAJ instruction, which automatically compares values from multiple replicated paths and outputs the majority result. This self-service approach eliminates the need for separate external voting circuits, reducing device complexity while maintaining fault tolerance.

Inventive Principle:

Principle #25Self-service

2Reliability

If multiple replicated signal paths are used, then reliability is improved, but loss of time increases due to voting operations

Engineering Contradiction:

Improvefault toleranceVSAvoidprocessing delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The majority voting operation is implemented as a native processor instruction that executes continuously alongside other computational operations. The voting logic is embedded in the instruction execution pipeline, allowing fault tolerance operations to proceed continuously without interrupting the normal flow of data processing, thus minimizing time loss.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The system maintains multiple replicated signal paths in parallel, performing computations simultaneously on all paths before the voting operation is needed. This preliminary parallel processing ensures that when the RMAJ instruction executes, all input values are already ready, eliminating waiting time and maintaining continuous useful action.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260003621A1Processor Employing Instruction That Performs A Bitwise Majority Vote Operation

Publication Date: 2026.01.01 APOGEE SEMICON INC

AI summary

A system includes a feedback control loop signal path. Circuitry of the signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs of the three slices execute identical programs of instructions, and are clocked in unison so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register bitwise majority vote” (RMAJ) operation. The instruction identifies a register of the slice, and the data content of this register is output via a bus to the two other slices. The DSP performs a bitwise majority vote on: 1) the data content of the register, 2) the data content of the corresponding register in each of the other two slices. The result of the bitwise majority vote is written into the register of the slice.