Bitwise Rotating Scan for Microelectronic Chip Testing

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Solution Overview

Problem

Conventional microelectronic chip testing methods, such as dedicated pin scanning and Multiple Scan Sections (MSS), face inefficiencies due to scan chain imbalances, leading to increased manufacturing test time and memory usage, and limited data collection capabilities when dealing with unbalanced scan chains.

Innovation Solution

A bitwise rotating scan method that divides microelectronic chip sections into subsets with predetermined latch sets, allowing for interleaving of alternating latch sets across scan chains, thereby optimizing scan time and memory usage while enabling efficient data collection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If dedicated pin scanning is used for each section, then diagnostics capability is improved, but test time and memory usage increase due to scan chain imbalances

Engineering Contradiction:

Improvediagnostics capabilityVSAvoidtest time

Core Design Contradiction:

Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The scan chains are divided into multiple groups, and scanning is performed in alternating fashion between groups rather than completing one entire scan chain before moving to the next. This segmentation allows parallel progress across multiple sections, reducing total test time while maintaining diagnostic capability through group-based monitoring

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The scanning process dynamically switches between different scan chain groups based on completion status. While one group is being scanned, the system transitions to scan the next group, creating a dynamic interleaved scanning pattern that optimizes resource utilization and reduces idle time

Inventive Principle:

Principle #15Dynamics

2Difficulty of detecting and measuring

If dedicated pin scanning is used for each section, then section-specific monitoring is improved, but tester memory requirements increase due to longest channel gating

Engineering Contradiction:

Improvesection monitoringVSAvoidtester memory

Core Design Contradiction:

Difficulty of detecting and measuringVSQuantity of substance

Solution Approach 1:

By dividing scan chains into groups and scanning them alternately, the system reduces peak memory requirements. Instead of holding all data from the longest scan chain in memory, the segmented approach processes and stores data from smaller groups sequentially, lowering the memory burden while preserving section-level diagnostic information

Inventive Principle:

Principle #1Segmentation

3Productivity

If Multiple Scan Sections method is used to scan each section one at a time, then scan bus access is optimized, but data collection capability is limited by fail data memory

Engineering Contradiction:

Improvescan bus efficiencyVSAvoidfail data collection

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The interleaved group scanning approach divides the scanning process into manageable groups that can be processed alternately. This segmentation enables more comprehensive data collection from multiple sections before memory fills up, as the system cycles through groups rather than being constrained to sequential section-by-section scanning

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The alternating scanning method maintains continuous useful action by switching between groups rather than idle while one group completes. This continuous cycling through multiple groups maximizes data collection from all sections within the available memory capacity, preventing information loss

Inventive Principle:

Principle #20Continuity of useful action

4Adaptability or versatility

If scan chains are made unbalanced to accommodate different section sizes, then section-specific scanning is improved, but overall test time is dictated by the longest channel

Engineering Contradiction:

Improvesection accommodationVSAvoidoverall test time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

By segmenting scan chains into groups and scanning them in an interleaved manner, the system accommodates different section sizes without being bottlenecked by the longest channel. Shorter groups complete faster and the system transitions to the next group, ensuring that overall test time is determined by the sum of all group scanning rather than being dictated solely by the longest individual channel

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10107860B2Bitwise rotating scan section for microelectronic chip testing and diagnostics

Publication Date: 2018.10.23 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

According to an embodiment of the present invention, a computer-implemented method for testing a microelectronic chip is described. The method may include dividing, via a processor running a scanning engine, a plurality of sections of the microelectronic chip. Each of the plurality of sections includes at least two latch sets in at least one scan chain. The method may further include determining, via the processor, based on the dividing, whether each of the plurality of sections fail a data test. The determining comprises interleaving the plurality of sections by scanning, via the processor, an alternating latch set from each scan chain in a first section, and scanning an alternating latch set from each scan chain in a second section.