Bit-Wise Selective Masking of X-Values in IC BIST
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Solution Overview
Problem
Existing built-in self-test (BIST) methods for integrated circuits (ICs) are inadequate in verifying proper operation under changing operational parameters and cannot effectively handle unknown or indeterminate X-values, leading to reduced reliability and coverage in functional fingerprinting.
Innovation Solution
A system and method for selective bit-wise masking of X-values in operational scan results, using a composite mask pattern generated and maintained internally within the IC, which is cyclically applied to prevent X-values from influencing the functional fingerprint, ensuring robust verification across varying operational conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external automated testing equipment is used to physically connect to IC ports for testing, then testing capability is provided, but device complexity and ease of operation deteriorate due to complicated physical mating or probing requirements
Solution Approach 1:
The IC device performs self-testing through built-in scan chains and test controllers that operate autonomously using existing internal resources, eliminating the need for external testing equipment physical connections while maintaining testing capability
Solution Approach 2:
Existing internal scan chains and logic elements are repurposed to perform both normal operational functions and self-testing functions, eliminating the need for separate external testing apparatus and reducing overall system complexity
2Ease of operation
If external testing apparatus is disconnected after fabrication testing, then IC deployment is enabled, but continuous validation capability is lost
Solution Approach 1:
The IC incorporates autonomous self-testing capability that operates independently without external apparatus, enabling continuous validation throughout the IC's operational lifecycle from fabrication through field deployment
Solution Approach 2:
The built-in self-test system enables continuous operational validation throughout the IC's entire lifecycle, maintaining testing capability from fabrication through deployment without interruption or external equipment dependency
3Loss of information
If X-values are allowed to propagate in scan results, then diagnostic data is preserved, but measurement precision deteriorates due to unknown or indeterminate values
Solution Approach 1:
The masking mechanism extracts and isolates X-values from scan results by applying composite mask patterns that identify and separate indeterminate values from valid diagnostic data, allowing precise handling of problematic bits while preserving useful information
Solution Approach 2:
Composite mask patterns serve as intermediary structures that mediate between raw scan results containing X-values and the final functional fingerprint, enabling systematic identification and management of indeterminate values without losing diagnostic information
4Measurement precision
If comprehensive masking of X-values is applied, then measurement precision is improved, but loss of information increases due to potential masking of valid diagnostic data
Solution Approach 1:
The composite mask pattern applies masking selectively at the individual bit level rather than uniformly across all scan results, enabling precise targeting of X-values while preserving valid diagnostic data through location-specific masking decisions
Solution Approach 2:
The system applies masking selectively only where X-values are identified through simulation analysis, avoiding excessive masking of valid data by limiting the masking action to specific problematic locations determined through prior computational analysis
5Manufacturing precision
If detailed simulation analysis is performed to generate mask patterns, then manufacturing precision is improved, but loss of time increases due to computational requirements
Solution Approach 1:
Comprehensive simulation analysis and mask pattern generation are performed in advance during the design and fabrication process, allowing detailed computational analysis to complete before production, thereby enabling precise masking without impacting operational time constraints
Solution Approach 2:
The mask pattern generation process is segmented into distinct phases including simulation, analysis, and pattern synthesis, allowing computational tasks to be distributed and optimized across different processing stages and resources
6Reliability
If chip resources are increased to improve BIST capabilities, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
Existing internal scan chains, logic elements, and operational circuitry are repurposed to perform self-testing functions, eliminating the need for dedicated additional test resources while maintaining comprehensive BIST capability
Solution Approach 2:
The IC uses its own operational resources and logic elements to perform self-testing, requiring no additional dedicated test hardware beyond what is already present for normal operation, thereby avoiding increased chip resource consumption
Data Source
AI summary
A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.