Silicon BJT Base Window Etching for QuBiC-SiGe HBT Compatibility
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Solution Overview
Problem
Conventional silicon-based BJT architectures using non-selective base SiGe technologies, such as the QuBiC family, are not directly compatible with the DPSA-SEG SiGe HBT structure, necessitating alternative BJT architectures that can be implemented using QuBiC process technology for integration with SiGe HBTs.
Innovation Solution
A silicon bipolar junction transistor (BJT) design featuring a polysilicon base layer with a window through a layer stack comprising SiGe, where the SiGe layer stack is etched at a late stage of the process, allowing for compatibility with a wide range of SiGe HBT process flows and reducing the number of photolithography stages, thereby improving process control and integration with SiGe HBTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional silicon-based BJT architectures using non-selective base SiGe technologies are used, then compatibility with existing QuBiC process technology is maintained, but direct compatibility with DPSA-SEG SiGe HBTs is not achieved
Solution Approach 1:
The SiGe layer stack is etched at a late stage of the process, after the polysilicon base layer and dielectric spacer are already in place. This preliminary positioning of the SiGe stack allows it to be selectively removed only where needed, enabling compatibility with DPSA-SEG HBTs without disrupting the established BJT process flow and reducing the number of additional photolithography stages required
2Productivity
If the SiGe layer stack is etched at an early stage of the process, then the BJT structure can be formed, but compatibility with a wide range of SiGe HBT process flows is reduced
Solution Approach 1:
The patent performs the SiGe layer stack etching as a preliminary step that is decoupled from the main BJT formation process. By etching the SiGe stack after the polysilicon base and dielectric spacer are formed, the process allows for optimized etch conditions and better control, while maintaining compatibility with various SiGe HBT process flows that may have different requirements for earlier process stages
3Manufacturing precision
If multiple photolithography stages are used for BJT fabrication, then precise patterning is achieved, but process complexity and manufacturing time increase
Solution Approach 1:
The patent merges the SiGe layer stack etching step with the existing BJT fabrication process by positioning it at a late stage where the polysilicon base and dielectric spacer are already formed. This integration allows the etch process to be combined with other process steps rather than requiring a dedicated photolithography stage, reducing the total number of lithography steps while maintaining precise patterning through the established process flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables direct compatibility with DPSA-SEG SiGe HBTs, optimizing the etch process and reducing complexity, allowing for efficient integration and improved control in the fabrication of both BJT and SiGe HBT devices on the same substrate.
Implementation Method 1
depositing a dielectric layer over the polysilicon layer
Implementation Method 2
a polysilicon emitter contact, at least partially filling the window within the liner and at least partially overlying the dielectric liner material on the upper surface of the polysilicon base layer, in electrical contact with the doped emitter region
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
Disclosed is a method of manufacturing a silicon bipolar junction transistor device, the method comprising a sequence of steps including: depositing a polysilicon layer (130) over at least a device region; depositing a dielectric layer (132) over the polysilicon layer; patterning a photoresist layer (222) and etching a window (240) in the dielectric layer and the polysilicon layer through an opening in the photoresist layer; etching a SiGe layer stack (118) through the window, to expose a silicon layer thereunder; patterning a further photoresist layer (144) to expose at least the window; and doping the silicon layer by ion implantation through the window to form a base region (152). A corresponding BJT device is shown in figure 9.