Bipolar Junction Transistor Leakage Reduction via Local Doping
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving efficient memory arrays due to high leakage current, low current driving capabilities, and parasitic effects in bipolar junction transistors, particularly in phase change and binary oxide unipolar resistive memories.
Innovation Solution
The use of bipolar junction transistors with reinforcement doping in the collector and base regions, self-aligned and localized at the bottom of shallow trench isolations, enhances current driving capabilities and reduces leakage, allowing for improved word line to word line isolation and larger memory array efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If bipolar junction transistors are used for selection devices in memory arrays, then current driving capabilities are improved, but leakage current increases and parasitic effects worsen
Solution Approach 1:
The patent applies local quality by implementing reinforcement doping specifically in the collector and base regions of the bipolar junction transistor. This localized doping enhancement improves the current driving capability and reduces leakage current in critical areas without adversely affecting other regions of the device, thereby resolving the contradiction between high current capability and low leakage.
Solution Approach 2:
The patent changes the doping parameters in the collector and base regions by introducing reinforcement doping. This parameter modification optimizes the electrical characteristics of the bipolar junction transistor, enhancing active current capability while reducing leakage current and parasitic effects, thus resolving the technical contradiction.
2Quantity of substance
If memory array size is increased, then storage capacity is improved, but parasitic effects from adjacent junctions increase
Solution Approach 1:
The patent applies local quality by providing word line to word line isolation through collector reinforcement dopants positioned between adjacent word lines. This localized isolation structure reduces parasitic effects between adjacent junctions, enabling larger memory arrays to be constructed without proportionally increasing parasitic interference.
Data Source
AI summary
A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced.