Integrated BJT-MOSFET Memory Cell for High Drive Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MOSFETs in memory devices require large sizes to provide high current, leading to increased layout area and reduced operation speed and performance as they shrink in size.
Innovation Solution
A semiconductor device and fabrication method that integrates a vertical bipolar junction transistor (BJT) with isolation structures and doped regions, allowing for high driving capability in a compact layout by utilizing the existing MOS process, enabling higher current delivery to memory cells without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFET size is reduced to minimize layout area, then device integration is improved, but driving capability and current provision deteriorate
Solution Approach 1:
The patent combines MOSFET and BJT structures into an integrated device where the BJT provides high current driving capability while the MOSFET maintains control functionality. This merging allows the device to deliver high current to memory cells without increasing the overall layout area, resolving the contradiction between miniaturization and driving capability.
Solution Approach 2:
The integrated device performs multiple functions: the BJT portion provides high current driving capability for memory cells, while the MOSFET portion provides voltage control and switching functionality. This multi-functionality allows a single compact device to replace what would traditionally require separate components, maintaining small layout area while achieving high driving capability.
2Area of moving object
If MOSFET size is reduced to improve integration, then device compactness is improved, but operation speed and performance deteriorate
Solution Approach 1:
By merging MOSFET and BJT structures, the device achieves high operation speed through the BJT's fast switching characteristics while maintaining compact size. The BJT's inherent speed advantage compensates for the reduced dimensions, allowing the device to maintain both compactness and high performance.
3Power
If MOSFET size is increased to provide high current, then driving capability is improved, but layout area increases
Solution Approach 1:
The device is segmented into distinct MOSFET and BJT regions, each optimized for its specific function. The BJT segment handles high current provision to memory cells, while the MOSFET segment handles control signals. This segmentation allows the high current function to be achieved without proportionally increasing the overall layout area, as each segment is optimized for its role.
Solution Approach 2:
The patent merges the high current capability of BJT with the control advantages of MOSFET in a single integrated structure. This combination allows the device to provide high current to memory cells using the BJT portion without requiring the entire device to be large, thus maintaining compact layout while achieving high current provision.
Data Source
AI summary
A method for fabricating a semiconductor device is described. A plurality of isolation structures is formed in a substrate. The isolation structures are arranged in parallel and extend along a first direction. A well of a first conductive type is formed in the substrate. A plurality of first doped regions of a second conductive type is formed in the well. Each of the first doped regions is formed between two adjacent isolation structures. A plurality of gates of the second conductive type is formed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is connected to one of the gates. A plurality of second doped regions of the first conductive type is formed in the well. Each of the second doped regions is formed in the first doped regions between two adjacent gates.